Stichting Imec Nederland

Imec Vzw

Nxp B.v.

University of Minnesota

Imec

Mario Konijnenburg

Seulki Lee

Erik Jan Marinissen

Nick Van Helleputte

Tobias Gemmeke

Christiaan Van Hoof

Victor Van Acht

Fokko Wieringa

Jacobus Verbree

Nahm Il Koo

Chun-Chuan Chi

Arjan Breeschoten

Vladimir Aleksandar Zivkovic

Luke Everson

Gijs Van Gestel

George Tsouhlarakis

Frank Van Der Heijden

Geert Seuren

Steven Oostdijk

Dwaipayan Biswas

A system for electrical impedance tomography comprises: a plurality of electrodes; a plurality of impedance measurement units, each being associated with two or more electrodes, and wherein each impedance measurement unit comprises a current generator for generating a stimulation current between the electrodes and an amplifier for amplifying a measurement voltage between the electrodes; wherein the system is configured to perform a plurality of impedance measurements, wherein, for each impedance measurement, one impedance measurement unit is set in a stimulation mode for providing a stimulation current into the object, and wherein the impedance measurement unit being set in the stimulation mode is switched among the plurality of impedance measurement units, and wherein each impedance measurement unit is configured to be set in a calibration mode during at least one of the plurality of impedance measurements.

System and method for electrical impedance tomography of an object, and an impedance measurement unit

A dialysis device () comprises: a dialyzer for exchange of substances between a blood flow and a dialysate flow in a dialysis area () of the dialyzer, wherein the dialyzer comprises a dialyzer membrane () for passing toxins in the blood flow to the dialysate flow through pores () of the dialyzer membrane (); and a capacitively coupled generator () for generating electromagnetic fields in the dialysis area () for loosening electrostatic bonds between toxins and proteins in the blood flow, wherein the generator () is capacitively coupled to the blood flow and to the dialysate flow on opposite sides of the dialyzer membrane, and wherein the dialysate membrane () is formed of a material having lower conductance than blood and dialysate such that a large electromagnetic field strength is provided across the pores () of the dialyzer membrane ().

Dialysis device and a control system for blood dialysis

A method of generating a model for generating a synthetic electrocardiography (ECG) signal comprises: receiving subject-specific training data for machine learning, said training data comprising a photoplethysmography (PPG) signal acquired from the subject and an ECG signal acquired from the subject, wherein the ECG signal provides a ground truth of the subject for associating the ECG signal with the PPG signal; using associated pairs of a time-series of the PPG signal and a corresponding time-series of the ECG signal as input to a deep neural network, DNN; and determining, through the DNN, a subject-specific model relating the PPG signal of the subject to the ECG signal of the subject for converting the PPG signal to a synthetic ECG signal using the subject-specific model.

Method for generating a model for generating a synthetic ECG and a method and system for analysis of heart activity

The disclosure relates to a memory access unit. One example embodiment is a memory access unit, for providing read-access to read an item from an arbitrary location in a physical memory, independently of addressable locations of the physical memory. The item includes a first number of bits and each addressable location of the physical memory includes a second number of bits. The second number of bits is different from the first number of bits. The memory access unit includes an address input, an address interpreter, an address output, a memory output, a data formatter, and a data output.

Memory access unit for providing access to an item from an arbitrary location in physical memory

A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.

Test access architecture for TSV-based 3D stacked ICS

An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyzer circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.

Method and apparatus for monitoring timing of critical paths

A test interface circuit operates with different types of core circuits. As consistent with various embodiments, the test interface circuit includes a test input register (TIR) configured to select an operating mode and a plurality of test point registers (TPRs). Each TPR is configured to control signals passed from the input port to a mixed-signal core circuit, responsive to the received test input signals and the operating mode selected by a TIR. In a static mode, each TPR provides serial access to digital inputs and outputs of a mixed-signal core circuit. In a bypass mode, each TPR bypasses TPR slices to preserve test time in response to the TPR being chained to other ones of the TPRs during integration of at least two mixed-signal cores.

Testing circuit and method

Growing community of inventors

Best, Netherlands

Mario Konijnenburg