Sun Microsystems, Inc.

Oracle America, Inc.

Oracle International Corporation

Other

Sun Micosystems, Inc.

Mario I Wolczko

Gregory M Wright

Matthew L Seidl

David M Ungar

William R Bush

Thomas Wuerthinger

Ilknur Cansu Kaynak Kocberber

Christopher A Vick

Adam R Talcott

Marc R Tremblay

Bernd J Mathiske

Antonio Cunei

Robert Cypher

Grzegorz Jan Czajkowski

Laurent Daynes

John P Petry

Nicolai Kosche

Bernd J W Mathiske

Laurent P Daynes

Michael L Van De Vanter

Mikhail A Dmitriev

Ross Charles Knippel

David C Schwartz

Douglas Norman Simon

Benjamin Lawrence Titzer

Gregorz J Czajkowski

Hannes E Payer

A tracing controller may utilize a binary execution trace mechanism to trace execution of compiled application machine code. The tracing controller may initiate hardware tracing to gather control-flow hardware traces of a method executing on a processor configured to generate hardware tracing information. The controller may generate a profile based on the hardware tracing information and initiate re-compiling or re-optimizing of the method in response to determining that the new profile differs from the previous profile. The controller may repeatedly profile and re-optimize a method until profiles for the method stabilize. Profiling and hardware tracing of an application may be selectively enabled or disabled allowing the controller to respond to later phase changes in application execution by re-optimizing, thereby potentially improving overall application performance.

Optimized recompilation using hardware tracing

A processor may implement position-independent memory addressing by providing load and store instructions that include position-independent addressing modes. A memory address may contain a normalized pointer, where the memory address stores a normalized memory address that, when added to an offset previously determined for the memory address, defines another memory address. The position-independent addressing mode may also support invalid memory addresses using a reserved value, where a load instruction providing the position-independent addressing mode may return a NULL value or generate an exception when determining that the stored normalized memory address is equal to the reserved value and where a store instruction providing the position-independent addressing mode may store the reserved value when determining that the memory address is an invalid or NULL memory address.

Processor supporting position-independent addressing

A processor may implement self-relative memory addressing by providing load and store instructions that include self-relative addressing modes. A memory address may contain a self-relative pointer, where the memory address stores a memory offset that, when added to the memory address, defines another memory address. The self-relative addressing mode may also support invalid memory addresses using a reserved offset value, where a load instruction providing the self-relative addressing mode may return a NULL value or generate an exception when determining that the stored offset value is equal to the reserved offset value and where a store instruction providing the self-relative addressing mode may store the reserved offset value when determining that the pointer is an invalid or NULL memory address.

Processor supporting self-relative addressing modes

Systems, computer instructions and computer-implemented methods are disclosed for implementing space- and time-efficient enumerations. An instance of an enumeration class may be created with a constant, plurality of enumerations. A plurality of objects corresponding to the respective enumerations may be stored in memory along with a lookup table indexed by respective ordinal values of the plurality of enumerations, the lookup table including respective references to the stored objects of the instantiated enumeration class. A reference to an enumeration may be stored in a memory location by storing an ordinal value of the enumeration. A determination may then be made to convert a stored ordinal value to a reference to an object, and responsive to the determination, the ordinal value may be loaded and used as an index into the lookup table to obtain the reference to the object corresponding to the enumeration.

Space- and time-efficient enumerations

A method of sampling instructions executing in a multi-threaded processor which includes selecting an instruction for sampling, storing information relating to the instruction, determining whether the instruction includes an event of interest, and reporting the instruction if the instruction includes an event of interest on a per-thread basis. The event of interest includes information relating to a thread to which the instruction is bound.

Instruction sampling in a multi-threaded processor

A garbage collection process performs garbage collection operations in an object-based memory system associated with a processing environment. The garbage collection process receives, at a first garbage collection unit, object references derived from root data from a processor associated with the first garbage collection unit. In addition, the garbage collection process processes, at the first garbage collection unit, the root data received from the processor associated with the first garbage collection unit. The garbage collection process also determines which object references derived from the root data are associated with a second garbage collection unit. Upon determining that an object reference is associated with a second garbage collection unit, the garbage collection process communicates information representative of the object reference to the second garbage collection unit associated with the object reference.

Methods and apparatus for marking objects for garbage collection in an object-based memory system

A method for managing data, including obtaining a first instruction for moving a first data item from a first source to a first destination, determining a data type of the first data item, determining a data type supported by the first destination, comparing the data type of the first data item with the data type supported by the first destination to test a validity of the first instruction, and moving the first data item from the first source to the first destination based on the validity of the first instruction.

Method and system for hardware-based security of object references

A method for managing an object watchpoint during a garbage collection cycle, including identifying an object having a field, where the object is associated with an original object location, where the field is associated with an original field location, and where the object and the field are located in a memory heap of a virtual machine memory, setting, within a debugger, the object watchpoint on the original field location, where the object watchpoint is a memory trap associated with the object, determining, after a relocation of the object by a garbage collector (GC), a new object location associated with the object, determining a new field location of the field based on the new object location, and setting, within the debugger, the object watchpoint on the new field location.

Tracking object fields using relocatable object watchpoints

A method for implementing a just-in-time compiler involves obtaining high-level code templates in a high-level programming language, where the high-level programming language is designed for compilation to an intermediate language capable of execution by a virtual machine, and where each high-level code template represents an instruction in the intermediate language. The method further involves compiling the high-level code templates to native code to obtain optimized native code templates, where compiling the high-level code templates is performed, prior to runtime, using an optimizing static compiler designed for runtime use with the virtual machine. The method further involves implementing the just-in-time compiler using the optimized native code templates, where the just-in-time compiler is configured to substitute an optimized native code template when a corresponding instruction in the intermediate language is encountered at runtime.

Method and system for implementing a just-in-time compiler

One embodiment of the present invention provides a system that accesses memory locations in an object-addressed memory system. During a memory access in the object-addressed memory system, the system receives an object identifier and an address. The system then uses the object identifier to identify a paged memory object associated with the memory access. Next, the system uses the address and a page table associated with the paged memory object to identify a memory page associated with the memory access. After determining the memory page, the system uses the address to access a memory location in the memory page.

Accessing memory locations for paged memory objects in an object-addressed memory system

A system and method are provided for inlining across protection domain boundaries with a system virtual machine. A protection domain comprises a unique combination of a privilege level and a memory address space. The system virtual machine interprets or dynamically compiles not only application code executing under guest operating systems, but also the guest operating systems. For a program call that crosses a protection domain boundary, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the applicable protection domains. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions reveal the protection domain in which they are to operate, and instructions corresponding to different domains may be interleaved.

Cross-domain inlining in a system virtual machine

A system and method are provided for inlining a program call between processes executing under separate ISAs (Instruction Set Architectures) within a system virtual machine. The system virtual machine hosts any number of virtual operating system instances, each of which may execute any number of applications. The system virtual machine interprets or dynamically compiles not only application code executing under virtual operating systems, but also the virtual operating systems. For a program call that crosses ISA boundaries, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the virtual ISA of the code. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions are configured and executed (or emulated) to perform as they would within the virtual ISA.

Growing community of inventors

Palo Alto, CA, United States of America

Mario I Wolczko