Sgsates Componenti Elettronici S.p.a.

Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Sgs Microelettronica Spa

Mario Foroni

Paolo Ferrari

Franco Bertotti

Benedetto Vigna

Flavio Francesco Villa

Marco Ferrera

Pietro Montanini

Maria T Gatti

Vincenzo Prestileo

Sergio Garue

An angular speed sensor comprises a pair of mobile masses which are formed in an epitaxial layer and are anchored to one another and to the remainder of the device by anchorage elements. The mobile masses are symmetrical with one another, and have first mobile excitation electrodes which are intercalated with respective first fixed excitation electrodes and second mobile detection electrodes which are intercalated with second fixed detection electrodes. The first mobile and fixed excitation electrodes extend in a first direction and the second mobile and fixed detection electrodes extend in a second direction which is perpendicular to the first direction and is disposed on a single plane parallel to the surface of the device.

Production method for integrated angular speed sensor device

The acceleration sensor is formed in a monocrystalline silicon wafer forming part of a dedicated SOI substrate presenting a first and second monocrystalline silicon wafer separated by an insulting layer having an air gap. A well is formed in the second wafer over the air gap and is subsequently trenched up to the air gap to release the monocrystalline silicon mass forming the movable mass of the sensor; the movable mass has two numbers of movable electrodes facing respective pluralities of fixed electrodes. In the idle condition, each movable electrode is separated by different distances from the two fixed electrodes facing the movable electrode.

Semiconductor integrated capacitive acceleration sensor and relative fabrication method

Semiconductor integrated capacitive acceleration sensor and relative

The collector area of a lateral PNP transistor may be incrementally increased during an electic testing step on wafer of an integrated circuit by purposely forming an auxiliary p-type diffused collector region having fractional dimensions near the primary collector region of the transistor and by permanently shorcircuiting the two regions by means of a 'Zener zapping' technique, by forcing a current through the inversely biased base-collector junction utilizing a suitable contact pad connected to the auxiliary collector region to create localized power dissipation conditions sufficient to melt the metal of the respective metal at the adjacent contacts and to form a permanent connection between the two metals. The technique is very useful for adjusting the value of the output current(s) in precision current generating circuits.

Method for incrementally increasing the collector area of a lateral PNP

This method of making an implanted resistor comprises the steps of implanting the resistor with ordinary techniques and deposition over the implanted resistor of a polysilicon layer having a set thickness and fully covering the resistor. Thus, the resulting resistor is unaffected by any subsequent thermal treatments and its value remains constant irrespective of any high potential metal layers or connections crossing it. The method affords in particular resistive values of the order of 1 kOhms/square.

Method of making an implanted resistor, and resistor obtained thereby

A semiconductor suppressor device consists of a structure including a P-type substrate, an N-type epitaxial layer, a first P-type diffusion region in the epitaxial layer, and a second N-type diffusion region in the first region. A first metallic layer which is in contact with the substrate and a second metallic region which is in contact with the first and the second regions form the terminals of the device. The epitaxial layer has at least one zone along the junction with the first region which has a higher concentration than the rest of the layer so that the conduction through a reverse-biased junction occurs in this zone. This enables the establishment of a highly accurate striking potential for the suppressor device.

Semiconductor overvoltage suppressor with accurately determined striking

This controlled electronic switching device for the suppression of transients can change over from a non-conductive state to a conductive state at lower triggering current levels than conventional devices while retaining unaltered its response characteristics to variations in the voltage applied thereacross. The device comprises a main switch which is triggered by a parallel-connected auxiliary switch having smaller junction areas and a higher capacitive current shunt resistance (resistance between base and emitter) than the main switch, thereby it turns on at lower control currents from the gate electrode for a given response to voltage variations.

Controlled electronic switching device for the suppression of transients

A lateral PNP transistor with concentric p-doped emitter and collector diffusion zones in an n-doped base layer epitaxially grown on a p-type silicon substrate, covered by a layer of silicon oxide, has emitter and collector electrodes in the form of metallic patches on the oxide layer overlying the respective diffusion zones and penetrating the oxide at limited contact areas. The metallic patches extend above an annular base-layer portion separating the two diffusion zones and symmetrically approach a circular centerline of this annular portion in order to guard against punch-through upon accidental polarity reversal of the collector/emitter voltage. A narrow peripheral gap in the collector electrode is traversed by an elongate metal strip which forms a radial extension of the emitter electrode leading to a supply terminal, the spacing of that strip from the gap edges substantially equaling the radial distance between the confronting peripheral boundaries of the two patches. If the diffusion zone of the collector is peripherally continuous instead of being interrupted in the region of the gap of the overlying electrode, the gap is bridged by a stratum of p-doped polycrystalline silicon embedded in the oxide layer and in conductive contact with the collector electrode on opposite sides of the gap, this stratum having an edge complementing the inner boundary of the metallic collector patch to a full circle around the emitter patch.

Integrated-circuit structure including lateral PNP transistor with

A silicon wafer incorporating several semiconductor components, among them a junction-type field-effect transistor (J-FET) of low pinch-off voltage connectable as a resistor, comprises a substrate of P-type conductivity with an insular layer of N.sup.+ conductivity penetrated by one or more enclaves of substrate material. Thereafter, a stratum of N-doped silicon is epitaxially grown on the substrate, with formation of rising zones above each enclave and around the buried N.sup.+ layer which are heavily doped with P-type impurities to act as source connections or sinkers for an FET channel formed by the enclave or enclaves and as a barrier junction surrounding a section of the N-doped stratum which becomes the gate of the FET while the substrate serves as the drain.

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Milan, Italy

Mario Foroni