Infineon Technologies Ag

Mario Di Ronza

Yannick Martelloni

Gunther Lehmann

Volker Sch&ouml;ber

Volker Schöber

Michael Diel

Olivier Picot

Embodiments of the invention provide a memory device comprising a non-volatile memory element, a read-out circuit for reading out an item of memory information stored in the memory element, a switching unit, by means of which a supply voltage can be applied to the read-out circuit, and a control unit, which has the capability of controlling the switching unit in a manner dependent on the memory information stored in the memory element.

Non-volatile memory device with controlled application of supply voltage

A method for repairing a memory comprising a Memory Built-In Self Repair (MBISR) structure comprises the steps of detection of defective storage cells, and redundancy allocation. The redundancy allocation step is carried out in such a way that it combines a row and/or column oriented redundancy repair approach with a word oriented redundancy repair approach. A Memory Built-In Self Repair (MBISR) device comprises at least one memory () with row and/or column redundancy, at least one row and/or column Memory Built-In Self Repair (MBISR) circuit (), and a word redundancy block (). Furthermore, a distributed MBISR structure as well as dedicated Column/Row MBISR circuits () are provided.

Memory built-in self repair (MBISR) circuits/devices and method for repairing a memory comprising a memory built-in self repair (MBISR) structure

An integrated memory and method for testing an integrated memory is provided herein. In order to test an integrated memory having a main data memory with a plurality of data memory units, a data memory unit is addressed and input test data for testing the addressed data memory unit are applied to the main data memory. The output test data are read out from the main data memory and compared with expected desired output test data in a self-test unit. Deviations detected during the comparison are buffer-stored in a redundancy analysis memory. These information items buffer-stored in the redundancy analysis memory are read out and transferred to a computing unit. In the computing unit, the defect positions in the output test data are identified, and a repair strategy is determined by means of redundant rows and/or redundant columns and/or redundant words provided. The redundant words required for the repair strategy are written to the redundancy analysis memory and activated.

Integrated memory and method for testing an integrated memory

A semiconductor memory device includes a plurality of integrated circuit modules each having a plurality of module elements and at least one adjustable module element. At least one fuse box is electrically connected to the plurality of integrated circuit modules. The fuse box has a plurality of programmable fuse elements, that, when programmed, adjust the adjustable module element.

Growing community of inventors

Munich, Germany

Mario Di Ronza