National Semiconductor Corporation

Apple Inc.

Other

Mario D Nemirovsky

Robert James Divivier

Alexander Perez

David V James

Christopher E Phillips

Narendra Sankar

Michael Francis O'Connor

Thomas W Thomson

Ralph W Haines

Wayne Yamamoto

Robert Walter Williams

Shailaja Chenumalla

HonKai John Tam

A pipelined processor in which the decoder can consume a portion of an instruction and hold that portion in sub-field shadow registers while retrieving the remainder of the instruction in a subsequent cycle or cycles. Each byte in a prefetch buffer is individually tagged such that the decoder can clear individual bytes in the prefetch buffer in order to allow additional instruction bytes to be prefetched before the current instruction is completely consumed and decoded by the decode stage. This allows for an optimal buffer size that is less than the maximum possible instruction length but large enough to hold a complete copy of the vast majority of instructions.

Tagged prefetch and instruction decoder for variable length instruction set and method of operation

A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers. Information bits about the instruction are added to the tables at no extra cost and enable the faster decode of the instruction. The present invention includes the decode of an instruction using an entry ROM, which contains information regarding the instruction that can directly be used in generating the decoder outputs. This information is also used in selecting the correct ROM entry, thus enhancing the flexibility of the decoder, and to dynamically generate a generic microcode entry. Thus, microcode space requirements are reduced. A generic microcode instruction is used for commonly used, similar macroinstructions. This avoids duplication of microcode instructions and thus reduces the required microcode space. The invention also includes the generation of a generic microinstruction dynamically by using the predecoded information selected from the entry microcode table. This makes the generic microinstruction flexible and hence, it can be efficiently be used for many instructions. An entry microcode table, used for the efficient decode of an instruction, contains predecoded information about the instruction apart from the regular microinstruction, which is used directly to generate the decoder outputs and to select the correct microcode entry, and also for the generation of the generic microcode entry. The invention also includes accessing the entry ROM and the .mu.ROM in parallel, using the same address which is generated from the opcode and ModR/M bytes, and selecting one of their outputs. Thus the two ROMs are used efficiently in that the required time and logic are reduced.

High speed, scalable microcode based instruction decoder for processors

An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions. Maximum performance is thereby achieved from the circuit functions accessed most frequently, while still achieving high performance from those circuit functions accessed less frequently. The IC may provided with a processor core with features that support In-Circuit Emulation (ICE).

In-circuit emulator for emulating native clustruction execution of a

The invention is a method and apparatus for conditionally nullifying a current instruction based on a first test value where the first test value can be set in one or more prior instructions and where the execution of the current instruction can set a second test value without affecting the first test value. The one or more prior instructions which set the first test value need not immediately precede the current instruction. In a preferred embodiment, a test value comprises multiple bits, each bit capable of representing a unique state. A mask is provided to select the bits which are being tested. Also, means are provided for specifying an logical operation to be performed on the test values. The invention permits multiple status test results to be saved and concurrently tested in a single branch instruction.

Method and apparatus for using condition codes to nullify instructions

An apparatus and method for efficiently generating the consecutive addresses needed to access misaligned or doubleword length data stored in the memory of a general purpose microprocessor. The apparatus shares the address generation operations between a small 3 bit adder, typically contained in the bus unit, and the execution unit. Control logic is used to determine whether a data misalignment situation exists based on the length of the data which is to be retrieved and the starting address of the data. When misalignment is indicated, the control unit acts to assign the address calculations to either the 3 bit adder alone or the execution unit together with the 3 bit adder depending upon how much the present address must be incremented to obtain the new addresses.

Apparatus and method for efficiently determining addresses for

Memory requests are pipelined to an external memory by forming a memory address during the same clock cycle that the associated instruction is executed, issuing a ready signal during the clock cycle that precedes the clock cycle in which information is output from an external memory, and directing information received from the external memory to a register file during the same clock cycle that the information is received. In addition, when an instruction requires the information that was requested by the previous instruction, the information is directed to an arithmetic logic unit (ALU) during the same clock cycle that the information is received. As a result, the cycle time required to retrieve information stored in a DRAM can be substantially reduced.

Pipelined microprocessor that pipelines memory requests to an external

A computer with a pipelined processor and code breakpoints for performing software debug operations includes prefetch and decode stages, debug address registers for storing code breakpoints representing addresses of preselected instructions, and two digital comparators. During the instruction prefetch phase of operation, the first comparator compares the 29 most significant bits �31:3! of the 32-bit prefetch instruction address against the code breakpoints stored in the debug address registers and produces a 1-bit signal indicating whether such comparison results in a positive match. Subsequently, during the decode phase of operation, the second comparator compares the three least significant bits �2:0! of the 32-bit prefetch instruction address and produces a 1-bit signal indicating whether such comparison results in a positive match. These two 1-bit signals are then logically ANDed, synchronized with bit 3 �2! of the 32-bit prefetch instruction address to ensure that such two 1-bit signals are based upon corresponding comparisons of the same prefetch instruction address.

Code breakpoint decoder

An efficient method for implementing string operations used to process blocks of data within a memory. The registers used to track the memory addresses are updated and committed before the outcome of a read or write address operation is known. In the event an exception occurs, exception handling hardware and microcode is used to restore the state of the registers to the condition they were in prior to the iteration which produced the exception. This reduces the number of microcode instructions required to implement the string operation, producing a faster cycling of the code through multiple iterations. The result is a more optimal code for string operations and a decrease in the time required to carry out the string instruction.

Method of implementing fast 486TM microprocessor compatible string

A method and apparatus for prefetching instructions in a pipelined processor including first and second prefetch buffers arranged in a two tier system. As instruction bytes are fetched from cache memory or external memory, those instruction bytes from memory for which there is space in the first level buffer are loaded therein, and, simultaneously, those valid instruction bytes in the second tier buffer for which there is room in the first tier buffer are also loaded into the first tier buffer. Those instruction bytes from memory for which there is not currently room in the first tier buffer are loaded into the second tier buffer. The second tier buffer is also used as a buffer for loading the instruction cache memory from the external memory.

Pipelined processor with two tier prefetch buffer structure and method

A microprocessor execution unit includes an arithmetic unit and an addressing unit. The arithmetic unit performs arithmetic and logical operations on operands. The addressing unit operates in conjunction with the arithmetic unit to calculate offsets, limits, and linear addresses in a single cycle.

Execution unit architecture to support X86 instruction set and X86

A circuit designates the values of an M bit first pointer and of an N+M bit second pointer. A first register circuit network holds the M bit first pointer, and a second register circuit network into holds an M bit portion of the N+M bit second pointer. A third register circuit network holds the remaining N bit portion of the N+M bit second pointer. A combiner circuit network, connected to receive the M bit first pointer from the first register circuit network, combines the received M bit first pointer with an externally provided data element length value to generate a new M bit first pointer. The combiner circuit network selectively generates a carry signal. The new M bit first pointer is selectively provided for loading into the first register circuit network and for loading into the second register circuit network as the M bit portion of the N+M bit portion of the second pointer. The remaining N bit portion of the N+M bit second pointer is received from the third register circuit network and, in response to the carry signal, one of the received remaining N bit portion and a modified remaining N bit portion is provided as a new remaining N bit portion for loading the new remaining N bit portion into the third register circuit network.

Circuit for designating instruction pointers for use by a processor

A method and apparatus for implementing a new imaging and image composition system based on the real world metaphor of surface absorption, reflection, and transmission where many layers of translucent and opaque objects are composed into a final image for output to a video display. The algorithms are a substitution for both 'Painter's algorithm' (the image composition technique traditionally used in computer graphic systems) and the alpha blending algorithms presently used in the computer and television industries for video special effects such as cross-fades between images, transparency, and color keying. In contrast to the prior art 'colored pixel' algorithms, this system is based on a light propagation metaphor that uses virtual light source illumination and the absorption, reflection, and transmission properties of the objects in the image to create the final screen image. Thus, instead of representing each picture element (pixel) by color components specified by a chosen color model (e.g., RGB, YUV, Lab, HSV, YIQ, HLS, CMY, CMYK, etc.), the pixels in the subject system are represented by six explicit transformation components (r.sub.1, r.sub.2, r.sub.3, t.sub.1, t.sub.2, t.sub.3) and three implicit transformation components (a.sub.1, a.sub.2, a.sub.3), wherein a, r and t refer to absorption, reflection and transmission, respectively, and the subscripts 1, 2 and 3 refer to the components of the chosen color model.

Image composition method and apparatus for developing, storing and

The invention is an instruction for locating the address of a specific character or value within a byte string of variable length. An offset into a portion of the string is specified and the portion of the string is searched for a first occurrence of the specific character beginning at the specified offset. If the specific character is found, then the existence of the specific character is indicated and an address or offset of the specific character is saved or otherwise indicated. If the specific character is not found, then the non-existence of the specific character is indicated and a convenient address or offset for referencing the next character immediately following the portion of the string already examined is saved or otherwise indicated. The specific character can have a length of one or more bytes and can be a pre-defined fixed value or a dynamic arbitrary value. The invention can execute in a time period comparable to performing an arithmetic instruction. Moreover, the invention can be combined with other load and store instructions, so that a copy operation can be performed by invoking this instruction sequence one or more times.

System for finding and setting address portion of variable-length

An associative memory is configurable to detect one of a plurality of relationships among a set of data, all within a number of cycles equal to the number of bits in the field of data upon which the sort is being executed. Because the memory is configurable, a single memory array can be used to accomplish a wide variety of results, either changing the relationship upon which the data is sorted on the fly, or providing a field programmable or mask programmable configuration input to adapt a given array design to a particular need. The array can be configured according to a configuration input to detect a relationship among fields of data stored in the memory selected from the group including 'greater than', 'greater than or equal to', 'less than', 'less than or equal to', 'equal to', a minimum and a maximum. Further, the memory system can be adapted to detect the minimum of a first field in a given row and the maximum of a second field in a given row in parallel.

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San Jose, CA, United States of America

Mario D Nemirovsky