International Business Machines Corporation

Mario A Marsico

John C Pescatore

Ronald J Cooper

Michael R Marr

Gilbert S Burrus, Jr

Paul D Sullivan

Richard Colbert Matlack, Jr

Robert L Smith, Jr

A communications concentrator and message multiplexer featuring direct access from the communications adapters to main memory via direct memory access means which eliminates the usual scanner or polling facility in a concentrator or multiplexer is described. A control microprocessor manages the allocation of memory, the conversion of message protocols and the servicing of interrupts to a plurality of port interface adapter microprocessors. The interface adapter microprocessors directly set up and control the DMA operation instead of having the DMA operation controlled by the control processor. One of the port adapters serves as a service adapter over a dedicated interface allowing a remote disgnostician access to internal registers in the control processor system, access to a dedicated read only storage for servicing, and logical interface to the main control processor for the purpose of entering instructions and directing functional operations to test each component of the system.

Scannerless message concentrator and communications multiplexer

Bus interconnection between the system busses of a multi-port communications controller and the busses of one or more multi-port adapters is facilitated with a new architecture for providing an interconnection controller. A programmably adjustable adapter and port interface controller is combined via a scannerless communications controller with a bus interconnection control logic that handles both DMA and interrupt mode data transfers for a large number of channels. The invention provides an improved apparatus and method for transferring data to or from numerous communication channel devices within a processor based communications system in such a manner that the optimum mode of data transfer may be individually programmed for each channel as system environment conditions demand.

Multiple port service expansion adapter for a communications controller

A multi-port communications controller and variable protocol adapter is described. The adapter utilizes a user programmable pluggable programming cartridge for defining individual communications port data service characteristics. The port data service characteristics are interpreted by a microprocessor which manages the interchange from port to port and to or from memory or a host system. Direct memory access or interrupt driven memory access modes of operation are individually selectable for each individual in bound and out bound communications channel. The communications protocols employed at each port may be of any standard type with the microprocessor in the adapter making the appropriate conversion. Communication speeds can be automatically recognized and matched for each port also. An arbitration processor for both DMA and interrupt driven data transfer services is included as the heart of the communications adapter design to provide the capability of individualized control over each in bound and out bound channel's mode of data transfer service for the optimum mode of operation for each port and type of data service required.

Multiple port communications adapter apparatus

Both DMA access and character interrupt driven access modes of service are provided to multiple communication ports by an integrated arbitration DMA/interrupt controller utilizing its own resident randomly accessible memory. Pipelined logic control architecture for handling service mode adaptations for each individual port and for managing memory accesses to main system memory enables the use of the random access memory with its inherent time delays in a manner that virtually eliminates the effect of any time delay in overall memory access throughput.

Multiple port integrated DMA and interrupt controller and arbitrator

In an arbitration apparatus and technique, the request lines from a plurality of potential requestors serve both as interrupt and DMA bus request signal lines to an arbitration device. The arbitration device selects among contending requestors on a priority basis and generates a grant signal interpreted by the requesting devices either as an interrupt grant or a bus grant depending upon whether or not an interrupt acknowledge signal is received. This effectively multiplexes the grant request lines from a plurality of requestors to greatly reduce interconnection complexity and cost. A single interrupt grant/bus grant multi-wire signal cable connects from the arbitration device to the individual requestors. A grant will appear on a single line thereof connected to an individual requestor that has been granted either an interrupt or access to the bus. Interrupt requests from the requestors are ORed together and simultaneously presented to a central controlling microprocessor. The arbitration device determines which requestor will be granted access and, under control of the central control microprocessor, the arbitrator gates an interrupt grant or a DMA grant signal to the device selected by the arbitration mechanism. The dual usage of the grant and request lines by the arbitration device represents a multiplexing feature to further reduce interconnections.

Multiplexed interrupt/DMA request arbitration apparatus and method

A multiprocessor array is described in which a central controlling microprocessor interfaces over commonly connected address and data busses to a plurality of peripheral microprocessors. A memory mapped I/O interface controls access to and from the busses for mutual receipt and exchange of signals between the processors and mutual exchange and receipt of data among the processors. The individual processors are selectively isolatable by a plurality of three state switch means connected between each processor and the interconnecting data and address busses. Error detection and control logic is connected via control lines to the individual processors and responsive to an error indication thereof, activates a multipoint error signal to all said microprocessors over a control line, which signal is interpreted by the processor then controlling said busses as a signal to deactivate its operation and as a signal at said control microprocessor to invoke an interrupt for analyzing the causes of said error. The control microprocessor can issue memory mapped I/O instructions to the individual three state selective isolation means and/or to any of the I/O microprocessors to respectively isolate the processors from said busses or to control said processors in an error analysis routine. The apparatus further includes a machine check register and a bus master register associated with said control microprocessor which registers can be written in by said control microprocessor and read from only by one of said I/O microprocessors.

Growing community of inventors

Cary, NC, United States of America

Mario A Marsico