Motorola Corporation

Freescale Semiconductor,inc.

Marino J Martinez

Ernest Schirmann

Julio C Costa

Saied N Tehrani

Jenn-Hwa Huang

Mark A Durlam

Olin L Hartin

Lawrence S Klingbeil, Jr

Adolfo C Reyes

Ernie Schirmann

Gordon M Grivna

Mariam G Sadaka

Herbert Goronkin

Nyles Wynn Cody

William J Ooms

Charles E Weitzel

Colby Greg Rampley

Mark R Wilson

Elizabeth C Glass

A method for fabricating an RF enhancement mode FET () having improved gate properties is provided. The method comprises the steps of providing () a substrate () having a stack of semiconductor layers () formed thereon, the stack including a cap layer () and a central layer () defining a device channel, forming () a photoresist pattern () over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating () an implant region () in the unmasked region, and (b) removing () the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.

Advanced RF enhancement-mode FETs with improved gate properties

An enhancement mode RF device and method of fabrication includes a stack of compound semiconductor layers, including a central layer defining a device channel, a doped cap layer, and a buffer epitaxially grown on a substrate. Source and drain implant areas, extending at least into the buffer, are formed to define an implant free area in the device channel between the source and drain. Source and drain metal contacts are positioned on an upper surface of the central layer. Several layers of insulation and dielectric are positioned over the device and a gate opening is formed and filled with gate metal. During epitaxial growth, the doped cap layer is tailored with a thickness and a doping to optimize channel performance including gate-drain breakdown voltage and channel resistance.

Enhancement mode RF device and fabrication method

An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.

Semiconductor device using a barrier layer between the gate electrode and substrate and method therefor

A semiconductor device includes a transistor (30, 51) having a gate electrode (15, 52) wherein the gate electrode (15, 52) has a highly resistive portion (24, 25, 55). The highly resistive portion (24, 25, 55) is integrated into the gate electrode (15, 52) and is coupled to the gate electrode (15, 52) using a via-less contact method.

Semiconductor transistor with stabilizing gate electrode

A semiconductor device (20) is formed on a compound semiconductor substrate (21). The semiconductor device (20) is oriented on the surface (40) of the compound semiconductor substrate (21) such that the physical forces that result from the thermal heating or cooling of the compound semiconductor substrate (21) are essentially equal. This orientation reduces the variability of the drain to source current of the semiconductor device (20) as the semiconductor device (20) is operated at different temperatures.

Compound semiconductor device having reduced temperature variability

A method for forming a metal pattern on a substrate (11) includes forming a dielectric stack (14) on a major surface (12) of the substrate (11) and forming a mask (22) on the dielectric stack (14). The dielectric stack (14) includes an aluminum nitride layer (16) serving as an etch stop layer between two dielectric layers (15, 17). An opening is formed in the dielectric stack (14) via successive etching. The etching of the dielectric layer (15) between the aluminum nitride layer (16) and the substrate (11) undercuts the aluminum nitride layer (16). A metal layer (30) is deposited on the major surface through the opening via sputtering. The metal layer (30) on the major surface is distinctively separated from a metal layer (34) on the edge of the opening. The mask (22) is dissolved in a solvent, thereby lifting-off a metal layer (34) deposited on the mask (22).

Method for forming a metal pattern on a substrate

A stable FET including a substrate structure with a doped layer formed as a portion of the substrate structure and defining an electrically conductive shielding region adjacent a surface of the substrate structure. A channel region is positioned on the shielding region and includes a plurality of epitaxial layers grown on the surface of the substrate structure in overlying relationship to the doped layer. A drain and a source are positioned on the channel region in spaced relationship from each other with a gate positioned in overlying relationship on the channel region between the drain and source. An externally accessible electrical contact is connected to the shielding region and to the source region to provide a path for the removal of internally generated charges, such as holes.

Stable FET with shielding region in the substrate

A method of fabricating semiconductor devices with a passivated surface includes providing first cap and etch stop layers and second cap and etch stop layers with a contact layer thereon so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually etched to define an electrode contact area and to expose the inter-electrode surface area. Portions of the first etch stop and cap layers remaining in the contact area are selectively removed and a metal contact is formed in the contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.

Method of fabricating semiconductor devices with a passivated surface

A method of fabricating semiconductor devices with a passivated surface includes providing a contact layer on a substrate so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other and to the substrate and the contact layer, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually and selectively etched to define an electrode contact area and to expose the inter-electrode surface area. The exposed inter-electrode surface area is passivated, either subsequent to or during the etching of the first layer. A metal contact is formed in the electrode contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.

A method of manufacturing a gate structure (19) for a semiconductor device (10) utilizes a dielectric layer (17) containing aluminum to protect the surface of a substrate (11) from residues resulting from deposition and etching of the gate structure (19). The gate structure (19) forms a refractory contact to the substrate (11), and the source and drain regions (26) are self-aligned to the gate structure (19). Semiconductor devices manufactured using methods in accordance with the present invention are observed to have a higher breakdown voltage and a higher transconductance, among other improved electrical performance characteristics.

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Phoenix, AZ, United States of America

Marino J Martinez