Nortel Networks Corporation

Ciena Corporation

Marinette Besson

Sadok Aouini

Stepan Iliasevitch

Jerry Yee-Tung Lam

Florin Pera

Matthew Baby Varghese

A delay locked loop (DLL) circuit includes inputs from M-phase clocks, M is an integer that is greater than or equal to 1; N delay cells in each of M separate delay lines, one delay line for each of the inputs from the M-phase clocks, and each of the N delay cells having a delay of k*&#x394;t, N is an integer, and k is an integer that is coprime with both N and M; N outputs for clock phases from the N delay cells; and an alignment circuit connected to outputs of the M separate delay lines and the inputs from the M-phase clocks and configured to provide phase locking.

Phase skipping technique for high-speed, high-phase number delay locked loop

A signal-level compensating system consists of a voltage-follower stage, a sensor and a output signal compensator. The voltage-follower stage includes a signal input for receiving an input signal, a signal output, and at least one transistor coupled between the signal input and the signal output for providing an output signal responsive to the input signal. The sensor provides a control signal indicative of variations in at least one of the power supply voltage and transistor characteristics of the transistor. The output signal compensator is coupled to the signal output and provides a compensator output signal responsive to the control signal for reducing the impact of the variations on the voltage-follower output signal.

Signal-level compensation for communications circuits

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Marinette Besson