Toshiba Memory Corporation

Kioxia Corporation

Marina Yamaguchi

Masumi Saitoh

Shoichi Kabuyanagi

Yuuichi Kamimuta

Shosuke Fujii

Takayuki Ishikawa

Kensuke Ota

Takashi Tachikawa

Masatoshi Yoshikawa

Kazuhiko Yamamoto

Kiwamu Sakuma

Takuya Konno

Riichiro Takaishi

Hiromichi Kuriyama

A semiconductor device according to an embodiment includes first to fifth interconnects, first to third memory cells, and a control circuit. The control circuit is configured to execute machine learning. Each of the first memory cells, the second memory cells, and the third memory cells includes a resistance changing element. In the machine learning, the control circuit is configured to: execute a write operation using a common write voltage to each of the second memory cells; and after the write operation, input input data to each of the first interconnects, and change a resistance value of at least one third memory cell of the third memory cells based on the input data and a signal output from each of the fifth interconnects based on the input data.

Semiconductor device

A memory device according to an embodiment includes a first conductive layer; a second conductive layer; a ferroelectric layer provided between the first conductive layer and the second conductive layer and containing hafnium oxide; a paraelectric layer provided between the first conductive layer and the ferroelectric layer and containing a first oxide; and an oxide layer provided between the paraelectric layer and the ferroelectric layer and containing a second oxide having an oxygen area density lower than an oxygen area density of the first oxide.

Memory device

A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.

Memory device and method having a control circuit configured to acquire information on a state of a control target, causes the control target to execute a read and write operation based on the state

A memory device of an embodiment includes: a first conductive layer; a second conductive layer; a first region provided between the first conductive layer and the second conductive layer, being in contact with the first conductive layer and the second conductive layer, and including a first metal oxide, the first metal oxide corresponding to at least one selected from a group consisting of tantalum oxide, lanthanum oxide, and hafnium oxide; and a first layer provided between the first conductive layer and the second conductive layer and including a second metal oxide different from the first metal oxide.

According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, and a first layer. A direction from the first conductive layer toward the second conductive layer is aligned with a first direction. The first layer is provided between the first conductive layer and the second conductive layer. The first layer includes a first region including titanium and oxygen, a second region including aluminum and oxygen and being provided between the first conductive layer and the first region, and a third region including aluminum and oxygen and being provided between the first region and the second conductive layer. A surface area in a first plane of a brookite region included in the first region is 58 percent or more of a surface area in the first plane of the first region. The first plane crosses the first direction.

According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.

Memory element

A memory device according to an embodiment includes a first conductive layer, a second conductive layer; and a first metal oxide layer provided between the first conductive layer and the second conductive layer. The first metal oxide layer includes titanium oxide, the first metal oxide layer has a first region and a second region, a mole fraction of anatase titanium oxide in the titanium oxide of the first region is a first mole fraction, and a mole fraction of anatase titanium oxide in the titanium oxide of the second region is a second mole fraction lower than the first mole fraction.

A semiconductor memory device according to an embodiment includes: a substrate having a surface extending in a first direction and a second direction intersecting the first direction; and a memory cell array disposed above the substrate, the memory cell array having: a first wiring line extending in the first direction; a second wiring line extending in a third direction intersecting the first and second directions; a third wiring line extending in the second direction; a memory cell including a first layer provided in an intersection region of the first wiring line and the second wiring line; and a select transistor including a channel layer provided between the second wiring line and the third wiring line, the first layer of the memory cell including a first material which is an oxide, and the channel layer of the select transistor including the first material.

Semiconductor memory device

According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.

According to one embodiment, a semiconductor memory device includes a semiconductor layer, a gate electrode, a metal containing portion, and an insulating portion. The semiconductor layer includes a first region and a second region. The second region has at least one of a region being amorphous or a region having a crystallinity lower than a crystallinity of the first region. The gate electrode is apart from the first region in a first direction. The first direction crosses a second direction connecting the first region and the second region. The metal containing portion is apart from the second region in the first direction. At least a part of the metal containing portion overlaps the gate electrode in the second direction. The insulating portion is provided between the gate electrode and the first region and between the metal containing portion and the second region.

Growing community of inventors

Yokkaichi, Japan

Marina Yamaguchi