Kabushiki Kaisha Toshiba

Mariko Kaku

Munehiro Yoshida

Kazuhide Yoneya

In a semiconductor memory device, sub-macros are connected sequentially onto an interface unit in which each sub-macro includes a data control unit connected to the interface unit through a global data line, a first memory block and a second memory block. The first memory block is connected to one side of the data control unit through a first local data line, and the second memory block is connected to the other side of the data control unit through a second local data line.

Semiconductor memory device

A semiconductor integrated circuit device, which enables impedance adjustment of a particular pad without affecting other pads or signal wirings or without the need for a design change in basic layout, has formed a number of elements and wirings on and in a silicon substrate and pads stacked thereon via an insulation film A particular pad is connected to a signal wiring formed in a bus line region and a capacitor-forming conductor behaving as an impedance adjusting conductor is formed to surround the pad A source line conductor is made in a space between the pad and the capacitor-forming conductor to encircle the capacitor-forming conductor Therefore, the pad capacitance can be increased by using the space around the pad other signal wirings and any others formed in the bus line region are not affected substantially. Since here is used the portion around the pad which is not used normally, the basic layout need not be changed.

Semiconductor integrated circuit device with pad impedance adjustment mechanism

To provide a semiconductor memory for synchronizing input of a command except for POWER-DOWN-EXIT or the like and write or read of data with an external clock and generating a column operation synchronous pulse having the same number as that of a burst length within the semiconductor memory by using an internal operation synchronous pulse having this external clock as a trigger and after activation of a column system circuit, using the internal operation synchronous pulse as a trigger. This semiconductor memory uses column pulse transfer signals, which are different between read and write to control a column system circuit.

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Yokohama, Japan

Mariko Kaku