Other

International Business Machines Corporation

Freescale Semiconductor,inc.

Marie Jeannette Sullivan

Jose Melanio Nunez

Robert Charles Podnar

Kun Xu

David B Kramer

Thomas Albert Petersen

Srinath Audityan

Thomas Albert Peterson

An integrated circuit device includes a processor core, and a controller. The processor core issues a command intended for a first thread of a plurality of threads. The controller initiates de-allocates hardware resources of the controller that are allocated to the first thread during a thread reset process for the first thread, returns a specified value to the processor core in response to the first command intended for the first thread during the thread reset process, drops responses intended for the first thread from other devices during the thread reset process, completes the thread reset process in response to a determination that all expected responses intended for the first thread have been either received or dropped, and continues to issue requests to other devices in response to commands from other threads of the plurality of threads and processing corresponding responses during the thread reset process.

Controller for managing a reset of a subset of threads in a multi-thread system

A data transfer unit is able to read data from a source at the source coherency granule size and write data at the destination coherency granule size even though the two granule sizes may be different. A data transfer unit has registers for storing the granule size information in preparation of performing a transfer of a data block between a source and a destination. The data block is transferred in sub-blocks. Except for the first and last sub-blocks, the sub-blocks, for a read, are sized to the source coherency granule size, which is the transfer size that has been optimized for the source. For the write, the sub-blocks are sized to the destination coherency granule size, which is the transfer size that has been optimized for the destination. Thus, both the read and the write are optimized even though the transfers themselves are among devices with different coherency granules.

Data transfer unit with support for multiple coherency granules

A system and method are provided for maintaining cache coherency in symmetric multiprocessor system by having logic for performing snoop queries separate from logic for performing snoop actions. This logic split permits increased throughput because pending snoop queries must no longer wait until snoop actions complete. Two state machines are disclosed: a pipeline state machine for snoop queries; and a snoop action state machine, for executing the split logic handling snoop requests.

Optimizing pipelined snoop processing

A computer system including a first multiprocessor system connected to a system bus and adapted to forward first and second load requests to the system bus where the first load request precedes the second load request. The system further includes a second multiprocessor system connected to the system bus. The second multiprocessor system includes a memory subsystem comprised of first and second cache levels arranged such that an operation that retrieves data from the first cache level is arbitrated through the second cache level before the data becomes available to the system bus. A snoop control state machine of the second multiprocessor system is adapted to stall arbitration of a second operation initiated in the second cache level responsive to the second load request until a first operation initiated in the first cache level responsive to the first load request has been arbitrated through the second cache level. In other words, new operations to a lower cache level are stalled until older operations pass the common arbitration point. The second multiprocessor is preferably adapted to send a data ready signal to the first multiprocessor when data associated with the first load request is available for transmission over the system bus.

Intervention ordering in a multiprocessor system

A memory subsystem for use with a multiprocessor computer system. The memory subsystem includes an operation block adapted for queuing an operation that misses in an L,cache of a multiprocessor. The multiprocessor is comprised of a set of processors, preferably fabricated on a single semiconductor substrate and packaged in a single device package. The memory subsystem further includes an arbiter that is configured to receive external snoop operations from a bus interface unit and a queued operation from the operation block. The arbiter is configured to select and initiate one of received operations. Coherency is maintained by forwarding the address associated with the operation selected by the arbiter to each of a plurality of coherency units. In this manner, external and internal snoop addresses are arbitrated at a single point to produce a single subsystem snoop address that is propagated to each coherency unit. Preferably, the operation block includes a load miss block suitable for queuing load type operations and a store miss block suitable for queuing store type operations. In one embodiment, the subsystem includes a unidirectional local interconnect suitable for connecting the memory subsystem and the set of processors. The coherency units preferably include the L,cache units of the set of processors, the operation block queues, and each stage of a memory subsystem pipeline.

Coherency maintenance in a multiprocessor system

Each processor (,) in a multiple processor system (,) includes a contingent response unit (,). Each contingent response unit (,) includes a pending operation unit (,) for identifying each pending address bus operation from the respective processor which specifies an address matching a snoop address from another processor. A snoop pipeline is associated with the pending operation unit (,) and includes a plurality of pipeline stages (,). Each snoop pipeline stage (,) has a contingent response flag location (,) and an identifier location (,). When a pending operation from the processor specifies an address which is matched by a younger operation from another processor, a contingent response flag control arrangement uses information from the pending operation unit (,) to set a contingent response flag in a first snoop pipeline stage (,). The contingent response flag control also stores in the first snoop pipeline stage (,) an identifier for the matched pending operation. If the matched pending operation finishes the address bus pipeline unsuccessfully and is itself retried, the contingent response flag control arrangement clears the contingent response flag in the snoop pipeline stage (,) in which the flag then resides. Otherwise the contingent response flag is used to provide a snoop response to the younger operation which matched the pending operation.

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Leander, TX, United States of America

Marie Jeannette Sullivan