Texas Instruments Corporation

Marie Denison

Sameer P Pendharkar

Philip Leland Hower

Guru Mathur

Taylor R Efland

Osvaldo Jorge Lopez

Pinghai Hao

Luigi Colombo

Juan Alejandro Herbsommer

Jonathan Almeria Noquil

Archana Venugopal

Joseph Maurice Khayat

Brian Ashley Carpenter

Binghua Hu

Seetharaman Sridhar

John Lin

Sridhar Seetharaman

Christopher Boguslaw Kocon

Robert Allan Neidorff

Hideaki Kawahara

Darvin R Edwards

Satyendra Singh Chauhan

Kezhakkedath Ramunni Udayakumar

Yongxi Zhang

Hiep Xuan Nguyen

Richard J Saye

Takahiko Kudoh

Theodore Sidney Moise

Brian Goodlin

Wei-Yan Shih

Keith Ryan Green

Lance W Barron

Ted S Moise

Umamaheswari Aghoram

Ubol Udompanyavit

Seetharaman Sridar

Hannes Estl

Yong Liu

Yizhong Xie

A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Trench gate trench field plate vertical MOSFET

A Multi-Chip Module (MCM) package includes a substrate having a plurality of metal terminals and at least a first die attach area. An encapsulant is around the substrate including on at least a portion of the topside and at least a portion of the bottomside of the package. At least a first device including at least two device terminals is attached face up on the first die attach area. At least a second device including at least two device terminals is flip-chip attached and stacked on the first device. At least one of the first device and second device include a transistor. At least one metal clip is between the first device and second device including a plurality of clip portions isolated from one another connecting at least one device terminal of each of the first device and second device to respective metal terminals of the plurality of metal terminals.

Multi-chip module including stacked power devices with metal clip

An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

Lateral MOSFET with buried drain extension layer

Trench gate trench field plate vertical mosfet

A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-&#xb0; K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Integration of heat spreader for beol thermal management

An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region and the drain contact, and a concurrently formed channel end diffused link between the buried drift region and the channel, where the channel end diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain end diffused link.

High voltage lateral extended drain MOS transistor with improved drift layer contact

An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

High voltage lateral DMOS transistor with optimized source-side blocking capability

An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

High voltage drain extension on thin buried oxide SOI

A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-&#xb0; K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Integration of backside heat spreader for thermal management

Growing community of inventors

Plano, TX, United States of America

Marie Denison