International Business Machines Corporation

Ultratech, Inc.

Marie-Claude Paquet

Timothy Harrison Daubenspeck

Michael A Gaynes

Wolfgang Sauter

Sri Muthuthamby Sri-Jayantha

Jeffrey Donald Gelorme

David L Questad

James L Speidell

Frank Louis Pompeo

Thomas Edward Lombardi

Son K Tran

Robert P Kuder, Ii

Daniel J Littrell

Jeffrey P Gambino

Timothy Dooling Sullivan

Christopher David Muzzy

Julien Sylvestre

Real Joseph Tetreault

Catherine Dufort

Marie-France Boyaud

Jon Alfred Casey

Ian D Melville

Peter Jeffrey Brofman

Jennifer V Muncy

Alexandre Blander

Tymon Barwicz

Paul Francis Fortier

Ekta Misra

Richard D Langlois

Elaine Cyr

Nicolas Boyer

Barnim Alexander Janta-Polczynski

Maxime Cadotte

Francis Santerre

An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Method and apparatus for strain relieving surface mount attached connectors

Systems and methods for nanofiller in an optical interface are provided. One system includes a fiber-optic interface for one or more optical fibers that includes a body including one or more grooves defined therein. At least one groove in the one or more grooves is configured to receive a corresponding optical fiber of the one or more optical fibers. The at least one groove of the one or more grooves is further configured to receive an adhesive to attach the body to a portion of the corresponding optical fiber. Further, fiber-optic interface includes a suspended structure associated with the at least one groove configured to couple light between the suspended structure and the corresponding optical fiber. Also, the adhesive comprises nanofiller configured to support an alignment of the suspended structure with the corresponding optical fiber within the at least one groove.

Nanofiller in an optical interface

The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed.

Low-stress dual underfill packaging

Methods and systems to method to determine an adhesion force of an underfill material to a chip assembled in a flip-chip module are provided. A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate. The method also includes forming a block from the layer of underfill material. The method further includes measuring a force required to shear the block from a surface of the flip-chip module.

Underfill adhesion measurements at a microscopic scale

A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.

Passivation layer surface topography modifications for improved integrity in packaged assemblies

Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Underfill flow guide structures and method of using same

Underfill flow guide structures and methods of using the same are provided with a module. The method includes mounting bumps on a substrate. The method also includes forming underfill flow guide structures on the substrate by patterning wires with an overlay of hard substance. The underfill flow guide structures are integrated with the substrate and formed between adjacent bumps. The underfill flow guide structures are further formed to uniformly guide underfill along the substrate during capillary underfill processing.

Embodiments of the invention provide a semiconductor chip having a passivation layer extending along a surface of a semiconductor substrate to an edge of the semiconductor substrate, and methods for their formation. One aspect of the invention provides a semiconductor chip comprising: a semiconductor substrate; a passivation layer including a photosensitive polyimide disposed along a surface of the semiconductor substrate and extending to at least one edge of the semiconductor substrate; and a channel extending through the passivation layer to the surface of the semiconductor substrate.

Passivation layer extension to chip edge

Underfill flow guide structures

A method, mold and apparatus for encapsulating and underfilling an integrated circuit chip assembly. The mold has a first portion and a second portion with the first portion having first and second cavities and at least one channel interconnecting the first and second cavities. The first cavity is adapted to enclose the integrated circuit chip on the substrate. A clamping force is applied to the first and second portions of the mold to clamp the substrate between them with the integrated circuit chip located in the first cavity. Vents exhaust air from the first cavity. Encapsulant is injected into the first cavity of the first portion at a location in the first portion remote from the point of connection of the channel such that encapsulant flows around and underneath the integrated circuit chip and through the channel into the second cavity to thereby underfill and encapsulate the integrated circuit assembly.

Transfer molding of integrated circuit packages

Growing community of inventors

Bromont, Canada

Marie-Claude Paquet