O2micro International Limited

Marian Udrea Spenea

Constantin Bucur

Laszlo Lipcsei

Marian Niculae

Serban Mihai Popescu

Viorel Alexandru Marinescu

George Simion

A transistor comprises a substrate of a first conductivity type, a drain region and a source region of a second conductivity type, a gate, a gate oxide layer, an adjustment implant region of the first conductivity type and a planar junction. The drain region and the source region are disposed in the substrate. The gate is placed over the substrate between the source region and the drain region. The gate is separated from the substrate by the gate oxide layer. The adjustment implant region is disposed under the gate oxide layer and in the substrate. A second doping concentration of the adjustment implant region is higher than a first doping concentration of the substrate. The adjustment implant region and the drain region in a predetermined shape form the planar junction with a surface curvature pointing towards the drain region to relax electrical field intensity at a location of the planar junction.

Metal oxide semiconductor (MOS) transistors with increased break down voltages and methods of making the same

A trimming locking circuit is provided for IC using a programmable fuse array for after-assembly trimming procedures. In one embodiment, a trimming locking circuit is provided for a single power supply input into the programmable fuse array. In another embodiment, a trimming locking circuit is provided to operate with two or more power supply inputs. The trimming locking circuit electrically isolates the programmable fuse array from over voltage conditions on the power supplies.

Circuit and method for trimming locking of integrated circuits

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San Jose, CA, United States of America

Marian Udrea Spenea