Intel Corporation

Marian Alin Petre

Murali Ramadoss

Ben J Ashbaugh

Vikranth Vemulapalli

Jonathan D Pearce

Altug Koker

Elmoustapha Ould-Ahmed-Vall

Subramaniam M Maiyuran

Varghese George

Nicolas C Galoppo Von Borries

Aravindh V Anantaraman

Valentin Andrei

Sungye Kim

William B Sadler

Abhishek R Appu

Joydeep Ray

Prasoonkumar Surti

Vasanth Ranganathan

Kamal Sinha

Scott R Janus

Mike MacPherson

Lakshminarayanan Striramassarma

Pattabhiraman K

Brent E Insko

Arthur Hunter, Jr

Yoav Harel

Shailesh Shah

Niran Cooray

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Systems and methods for improving cache efficiency and utilization

Embodiments are generally directed to thread group scheduling for graphics processing. An embodiment of an apparatus includes a plurality of processors including a plurality of graphics processors to process data; a memory; and one or more caches for storage of data for the plurality of graphics processors, wherein the one or more processors are to schedule a plurality of groups of threads for processing by the plurality of graphics processors, the scheduling of the plurality of groups of threads including the plurality of processors to apply a bias for scheduling the plurality of groups of threads according to a cache locality for the one or more caches.

Thread group scheduling for graphics processing

Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.

Preemptive page fault handling

Growing community of inventors

San Mateo, CA, United States of America

Marian Alin Petre