International Business Machines Corporation

Maria Lorena Pesantez

Alper Buyuktosunoglu

Pradip Bose

Michael Stephen Floyd

David Henry Wilde

Michael K Gschwind

Giles R Frazier

Bret Ronald Olszewski

Gregory Scott Still

Emrah Acar

Bishop Chapman Brock

James Wilson Bishop

Ram Raghavan

Dan Buerkle

Gayathri Mohan

A computer-implemented method for of constrained carries on speculative counters includes providing one or more speculative counters having an upper portion of most significant bits partially embedded in a random-access memory (RAM) array, and a pre-counter portion external to the RAM array having a plurality of least significant bits. The one or more speculative counters are configured to count a plurality of events of interest during a processor core instruction execution. A carry output from the pre-counter portion to the RAM array is suppressed for a duration of a speculative event period.

Constrained carries on speculative counters

An approach is provided in which a first core broadcasts a cache line request in response to detecting a cache miss corresponding to a first virtual central processing unit (VCPU) executing on the first core. Next, the first core receives a cache line response from the second core responding to the cache line request that includes tag extension data. The first core determines a cache miss type of the cache miss based on the tag extension data and, in turn, sends the cache miss type to a hypervisor that utilizes the cache miss type during a future VCPU dispatch selection.

Virtual processor cache reuse

A system includes memory and a hardware processor. The memory includes a load-monitored region register (LMRR) and a sampled data address register (SDAR). The hardware processor is configured to perform a garbage collection process that reclaims unused objects of the memory. The hardware processor further executes a performance monitoring process that provides information indicating a utilization of an instruction performed by the hardware processor. The SDAR is configured to store first data generated according to the garbage process and second data generated according to the performance monitoring process.

Multi-section garbage collection system including shared performance monitor register

The embodiments provide an assigned counter of a first set of counters and stores a value for an activity of a set of activities forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. A power manager manages the first set of counters, receives a set of activities to be monitored for a unit, groups the portion into subsets based on at least one of a frequency of occurrence of each activity and power consumption for each activity, sums the stored values corresponding to each activity in each subset to reach a total value for each subset, multiplies the total value of each subset by factor corresponding to the subset to form a scaled value for each subset, and sums the scaled value of each subset to form a power usage value.

On-chip power proxy based architecture

A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.

Dynamically tune power proxy architectures

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Austin, TX, United States of America

Maria Lorena Pesantez