Harris Corporation

Maria Laprade

Timothy F Dyson

Matthew C Cobb

Thomas L Sterling

A Serially Concatenated Convolutional Code (SCCC) decoding system includes an outer decoder module (), permutation module (), and data store (). The outer decoder module is configured to generate a first sequence of soft-decision bits x[n] for n=0, 1, 2, . . . , N&#x2212;1. The permutation module is configured to permute the first sequence of soft-decision bits x[n] to generate a second sequence of soft-decision bits y[n]. The first sequence of soft-decision bits x[n] is generated by the outer decoder module in accordance with a mapping v[n]. The second sequence of soft-decision bits y[n] is generated for communication to an inner decoder module (). The data store contains a mapping v[n]. The mapping v[n] satisfies a mathematical equation v[k+m&#xb7;(N/M)] modulo (N/M)=v[k] modulo (N/M) for m=0, . . . , M&#x2212;1 and k=0, . . . , (N/M&#x2212;1). (NM) is an integer.

Serially concatenated convolutional code decoder with a constrained permutation table

A method is provided for performing a MAP probability decoding of a sequence R(n) including N bits of encoded data. The method includes the steps of: (a) generating a sequence rof sot-values by processing the sequence R(n); (b) performing a forward recursion by computing alpha values &#x3b1;utilizing the soft-decision values; (c) performing a backward recursion by computing beta values &#x3b2;utilizing the soft-decision values; and (d) performing an extrinsic computation by computing probability values p'. The alpha values &#x3b1;are relative log-likelihoods of an encoding process arriving at various states. The beta values &#x3b2;are relative log-likelihoods of the encoding process arriving at various states. The probability values p&#x2032;represent a set of probabilities indicating that each data bit of an input sequence dhad a value equal to zero or one. The sequence R(n) represents an encoded form of the input sequence d.

Maximum a posteriori probability decoder

A serial concatenated convolutional code (SCCC) decoder is provided. The SCCC decoder includes an input buffer memory one or more processing loop modules, and an output buffer memory. Each processing loop module includes a permutation module, inner decoding engines, a depermutation module, and outer decoding engines. The depermutation module includes a concatenating device and two or more depermutation buffer memories. The concatenating device is configured for writing a codeword segment containing a plurality of soft-decision bits to each of the depermutation buffer memories in a single write operation. The permutation module also includes a concatenating device and two or more permutation buffer memories. The concatenating device is configured for writing a codeword segment containing a plurality of soft-decision bits to each of the depermutation buffer memories in a single write operation.

Serial concatenated convolutional code decoder

A decoding system () is provided. The decoding system is comprised of two or more serial concatenated convolutional code (SCCC) decoders (-) operating in parallel. The SCCC decoders are configured to concurrently decode codeblocks which have been encoded using a convolutational code. The decoding system is also comprised of a single common address generator () and data store (). The address generator is responsive to requests for data needed by two or more of the SCCC decoders for permutation and depermutation. The data store is comprised of two or more memory blocks (-). The SCCC decoders concurrently generate requests for two or more different data types. Selected ones of the different data types are exclusively stored in different ones of the memory blocks. Selected ones of the different data types are comprised of data which is requested at the same time by a particular one of the SCCC decoders.

Parallel arrangement of serial concatenated convolutional code decoders with optimized organization of data for efficient use of memory resources

A serial concatenated convolutional code (SCCC) decoder is provided. The SCCC decoder is comprised of an input buffer memory (), one or more processing loop modules (), and an output buffer memory (). Each processing loop module is comprised of a permutation module (), an inner decoder module (), a depermutation module (), and an outer decoder module (). The inner decoder module is subdivided into two (2) or more inner decoding engines (-) configured for concurrently performing a decoding operation based on an inner convolutional code. The outer decoder module is subdivided into two (2) or more outer decoding engines (-) configured for concurrently performing a decoding operation based on an outer convolutional code. The inner convolutional code and the outer convolutional code are designed in accordance with a maximum aposteriori probability based decoding algorithm.

An activity monitor for monitoring activity on a bus connecting a plurality of processors, monitors the bus to determine the bus master and other bus activities. In response thereto, predetermined memory locations are enabled to count events on the bus or calculate time spans for various bus activities.

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Palm Bay, FL, United States of America

Maria Laprade