Compaq Computer Corporation, Inc.

Other

Maria L Melo

Khaldoun Alzien

Randy M Bonella

Todd J Deschepper

Paul R Culley

Hung Q Le

David J Maguire

James R Reif

David J Delisle

Brian B Tucker

Robert A Lester

Arnold Thomas Schnell

Robert C Elliott

Mark E Taylor

Michael P Moriarty

Roger E Tipley

Jeff W Wolford

Gregory N Santos

Karl N Walker

Jeffrey T Wilson

Shaun V Wandler

A bridge logic unit provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to memory bus, and a peripheral device coupled to a peripheral bus, such as a PCI bus. To maintain coherency, the bridge logic unit disables write posting in certain specific situations, and flushes posted write transactions before allowing certain read requests to be serviced. More specifically, in one embodiment when a PCI device performs a read to main memory, which may be implemented within the bridge as delayed read, the bus bridge blocks CPU to PCI transactions and flushes any posted CPU to PCI transactions pending in the bridge. The bus bridge enables CPU to PCI posting after the pending CPU to PCI transactions have been flushed and after the snoop phase of a snoop cycle corresponding to the memory read operation completes. In a further embodiment, prior to performing a PCI read cycle on behalf of a read cycle initiated by the microprocessor, the bus bridge determines whether any PCI to memory transactions are pending in the PCI slave transient write buffer. If any posted write transactions reside in the PCI slave transient write buffer, the bus bridge retries the read cycle on the processor bus and blocks any subsequent posting of write transactions to memory from the PCI bus. When the pending PCI to memory transactions have been flushed from the PCI slave transient write buffer, and the microprocessor reattempts the read, the read cycle is initiated on the PCI bus. At this point, PCI to memory write posting is re-enabled.

System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations

A computer having a bus interface unit coupled between a CPU bus and a PCI bus and/or a bus interface unit coupled between a PCI bus and memory and or I/O space. The clocking to the configuration space of the bus interface unit can be inhibited to conserve power in two ways. The first approach relies on an input/output address space containing a configuration address register. An enable bit or flag within the configuration address register can be set to allow a determination of the various PCI devices and to configure those devices linked to the PCI bus. Subsequent to computer boot up or initialization, the enable bit can be disabled to disallow further accesses to the configuration address space of the PCI device or PCI compliant bus interface unit. Disabling the enable bit further inhibits or disconnects a clocking signal from sequential logic within the configuration address space to minimize power consumption of the north bridge during its normal operation. In the second approach, the clocking to the configuration space is automatically enabled and disabled as needed by the bus interface unit to transfer data to and from its configuration registers. Removing the clocking signal, in either approach, minimizes power consumption allowing additional functions to be added to the mobile PC.

Configuration logic within a PCI compliant bus interface unit which can be selectively disconnected from a clocking source to conserve power

A computer is provided having a bus interface unit coupled between a CPU bus and a mezzanine bus, or PCI bus. The bus interface unit includes a plurality of input buffers which can be selectively connected and disconnected in a dynamic fashion according to active and inactive signals forwarded thereto. Signals forwarded to the bus interface unit from the CPU are classified according to the transaction phase of CPU bus activity. If signals associated with one particular transaction phase are active, then input buffers attributed to signals of other transaction phases can be deactivated. It is preferred that input buffers associated with signals of a request and arbitration phase be maintained active and coupled to power regardless of the present transaction phase unless the computer enters a powered down mode, such as sleep, idle or standby.

Device and method for dynamically reducing power consumption within input buffers of a bus interface unit

A computer system includes a secondary bus bridge device in a portable computer and a another secondary bus bridge device in an expansion base to which the portable computer connects (docks). A peripheral in the expansion base may initiate a delayed cycle to read or write data to memory through a primary bus bridge device that also couples to a CPU. Both secondary bus bridge devices include an arbiter for controlling arbitration of a peripheral bus that connects both secondary bridge devices. The arbiter in the secondary bridge of the portable computer determines which of the arbiters will have arbitration control of the expansion bus to run cycles. When read data is available, in the case of a delayed read cycle initiated by a peripheral device in the expansion base, the primary bridge strobes a delayed cycle control signal to the arbiter in the portable computer which then gives arbitration control to the arbiter in the expansion base.

Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base

A computer system includes a bus bridge which provides an interface between a main memory and a peripheral bus such as a PCI bus. A peripheral bus interface unit is provided which supports delayed transactions. When a PCI bus master effectuates a read cycle to read data from main memory on the PCI bus, the peripheral bus interface detects the read cycle and terminates or retries the transaction on the PCI bus. The peripheral bus interface further requests the read data from main memory and places the read data in a buffer. When the PCI master device re-attempts the read transaction, the peripheral interface provides the read data directly from its delayed read buffer. When the peripheral bus interface retries the PCI master that establishes a delayed read operation, the peripheral bus interface asserts a control signal referred to the delayed cycle signal. A PCI arbiter which controls ownership of the PCI bus receives the delayed cycle signal and, in response to its assertion, lowers a level of arbitration priority provided to the PCI master establishing the delayed read. In one embodiment, the PCI arbiter inhibits ownership of the PCI bus by the master establishing the delayed read in response to assertion of the delayed cycle signal. When the peripheral bus interface receives the read data and is ready to deliver it to the PCI bus, the delayed cycle signal is deasserted (or strobed). The PCI bus arbiter detects this deassertion (or strobing) of the delayed cycle signal and responsively raises a level of arbitration priority to the PCI master establishing the delayed read. In one implementation, upon detecting the deassertion of the delayed cycle signal, the PCI bus arbiter provides a highest level of arbitration priority to the PCI master establishing the delayed read. The delayed read operation then completes when the PCI master re-initiates the read cycle. The optimized arbitration technique may similarly be employed during other delayed transactions, such as memory writes, I/O read or writes, and configuration reads or writes.

Computer system employing optimized delayed transaction arbitration technique

A computer system having a processor, a microcontroller, a flash ROM is provided with an address remapper for handling warm-boot events, and an arbiter for selectively assigning the ownership of the flash ROM to either the microprocessor or the microcontroller. The arbiter assigns the flash ROM initially to the microcontroller when power is initially provided to the system. After the flash ROM boots up and checks the integrity of the flash ROM and updates the content of the flash ROM with valid firmware if necessary, the microcontroller releases the flash ROM to the microprocessor to enable the computer system to proceed with the normal boot-up process. In this process, various system self tests are performed. Next, the microprocessor copies or shadows one or more portions of the flash ROM BIOS into a main memory array. After the shadow operation, the processor sets a remap bit to indicate that the ROM BIOS content has been copied into the main memory array. The setting of the remap bit enables the remapper to deflect accesses to the flash ROM. The restarting of the clock signal to the microcontroller to switch the ownership of the flash ROM back to the microcontroller. In the event that the microprocessor needs to regain access to the flash ROM contents, the microprocessor writes to the mailbox register of the arbiter to request access to the flash ROM. The microprocessor waits for a confirmation from the arbiter that the microcontroller is entering an idled mode. Next, the microprocessor halts the clock of the microcontroller. These events cause the microcontroller to float or tristate the signal lines going from the microcontroller to the flash ROM such that the microprocessor can drive the signal lines without any conflict potentials. In this manner, the microprocessor can still access the shared flash ROM after it has booted up. Thus, the system cost is reduced, the system reliability is enhanced, while the system accessibility to the flash ROM after the boot-up period is still preserved.

Flash ROM sharing between processor and microcontroller during booting

A computer is provided having a bus interface unit which is coupled between a peripheral bus and a dedicated graphics bus. The graphics bus can be linked to the bus interface unit by an AGP, while the peripheral bus can be linked to the bus interface unit by a PCI. Arbitration for the AGP bus can determine when mastership is granted to an AGP master (i.e., graphics accelerator/controller). Until mastership is granted, the AGP target is powered down to a low power state where power consumption within the bus interface unit is minimal. It is not until the AGP master achieves mastership that the graphics target (core logic and memory controller) within the bus interface unit is placed in an operational (fully powered) state. The computer therefore employs a bus interface unit which can be dynamically switched from a high power state to a low power state and vice versa, depending upon accesses to the graphics target.

Device and method for reducing power consumption within an accelerated

A computer system includes a CPU and a memory device coupled through a North bridge logic device. The computer also includes a South bridge logic device coupled to the North bridge by a primary bus. The South bridge waits as long as possible before asserting a flush request (FLUSHREQ) control signal to the North bridge. The South bridge asserts the FLUSHREQ signal to the North bridge after a peripheral device coupled to the South bridge requests access to the primary bus to run a cycle. The South bridge first flushes a write queue before asserting the FLUSHREQ signal to the North bridge. In response to the FLUSHREQ control signal, the North bridge flushes one or more of its own internal write queues in preparation for the upcoming peripheral device cycle. By flushing its own internal write queue before asserting FLUSHREQ to the North bridge, the South bridge reduces the amount of time that the CPU will be prevented from accessing the primary expansion bus while the peripheral device attempts to run a cycle on the primary bus. An alternative embodiment of the invention includes a pair of South bridges, one South bridge in a laptop computer and the other South bridge in an expansion base to which the laptop computer mates.

Computer system with bridge logic that reduces interference to CPU

A PCI bridge is configured to perform delayed read operations in response to a memory read initiated on the PCI bus. Normally, the PCI bridge is configured to discard delayed read data read from main memory following a predetermined discard count time after the PCI master establishing the delayed read operation is retried on the PCI bus. The computer system further includes a secondary bus bridge such as an ISA bridge for providing an interface between the PCI bus and an ISA bus. When an ISA device desires to read data from the main memory, the ISA bridge asserts a flush request signal. The PCI bridge responsively flushes any pending CPU to PCI transactions pending within the PCI bridge. When the flushing operation is complete, the PCI bridge asserts an acknowledge signal. A PCI arbiter for arbitrating ownership of the PCI bus may increase a level of arbitration priority provided to the ISA bridge in response to assertion of the acknowledge signal. The PCI bridge is advantageously configured to decrease the time associated with discarding of the delayed read data when the acknowledge signal is asserted.

Dynamic delayed transaction discard counter in a bus bridge of a

Arbitration circuitry in a computer system having a plurality of arbiters for arbitrating requests from bus masters on a PCI bus and an EISA bus. Each of the PCI and EISA buses have a plurality of masters. The PCI bus utilizes a modified LRU arbitration scheme, while the EISA bus utilizes a rotating priority scheme. The arbiter on the EISA bus includes a first level of arbitration and a second level of arbitration. The first level is assigned a plurality of requester types to determine the priority between the requestor types. Certain of the first level requestor types include a plurality of devices. If one of those certain requestor types wins priority on the first level arbitration cycle, a second level arbitration is performed to determine the priority between the plurality of devices.

Dual arbiters for arbitrating access to a first and second bus in a

A PCI repeater coupled between a primary bus and a secondary bus includes logic to allow downstream and upstream bursting across the repeater. The PCI repeater echoes transactions in either an upstream or downstream direction, and does not need any additional address decode logic. The buses are coupled to an arbiter so that only one bus master has control of the bus. During a burst operation, the PCI repeater causes the arbiter to cease providing grant signals to prospective bus grantees. The signal is removed only after the transaction has completed on both sides of the PCI repeater to ensure that the PCI repeater is ready for a next transaction.

PCI to PCI bridge for transparently completing transactions between

To assure that memory and/or I/O cycles will run correctly after a PCI device configuration cycle that changes memory and/or I/O mapping, in a multi-processor P6 computer system that pipelines instructions. The memory and I/O cycles are suspended on the processor bus until the configuration cycle has been completed. A signal is generated within the address decode logic to prevent address decoding from taking place if a PCI device is being configured. During the configuration transactions, other pipelined transaction cycles are snoop stalled until the PCI configuration write has been completed.

Preventing corruption in a multiple processor computer system during a

An arbiter which allows retried requests to have high priority in subsequent arbitrations by not changing priority on a granted, but aborted, access to the bus and yet prevents the aborted requestor from thrashing the bus by masking its bus request signal until the data is available. Further, should an access to main memory be retried, all bus requests except the one from the memory system are masked to provide the memory system the highest effective priority to allow any flushing operations to occur. The masking of the various bus requests allows the arbiter to control access to a PCI standard bus without requiring that specific signals be added. The arbiter further includes modified priority LRU techniques and provides a locking requestor with an additional, highest priority position if retried.

Bus master arbitration circuitry having improved prioritization

An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.

Growing community of inventors

Houston, TX, United States of America

Maria L Melo