Xilinx, Inc.

Maria George

Hing Yan To

Chandrasekaran Nageswara Gupta

Austin S Tavares

John J Rinck

Juan Wang

Lakshmi Gopalakrishnan

Some examples described herein relate to a design system and a method for printed circuit board (PCB) design. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to provide a workspace in a user interface in which a PCB design comprising multiple layers is capable of being created; provide a list of layout templates in the user interface; and provide an insert function, via the user interface, configured to insert a selected layout template of the list of layout templates into the workspace to be included in the PCB design. Each layout template of the list of layout templates is a tile layout that includes a layout component and metal lines that extend to one or more edges of the tile layout.

Printed circuit board (PCB) modular design

Methods and apparatus are described for pinning out multiple memory devices using shared conductors therebetween and providing multiple chip select signals to indicate to which of the memory devices address signals on the shared conductors apply. In the case of a clamshell configuration with a top memory device having a corresponding bottom memory device and shared vias coupled therebetween, sharing two address signals for each shared via in this manner reduces the total number of vias used, thereby reducing routing congestion and enabling the addition of ground vias around the shared vias to reduce crosstalk for the address signals.

Effective clamshell mirroring for memory interfaces

Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous interface, where the data signal and the timing signal are provided in association with one another. The timing signal is frequency divided by frequency divider to provide an enable signal. Data of the data signal is captured responsive to the timing signal and the enable signal, where the data captured is in a time domain of the timing signal. A data valid signal is generated from the enable signal and an internal clock signal, where the data valid signal is internally timed without having to determine a system level delay. The data is recaptured responsive to the internal clock signal and the data valid signal, where the recaptured data is in a time domain of the internal clock signal.

Growing community of inventors

San Jose, CA, United States of America

Maria George