Altera Corporation

Maria D'Souza

Philippe Molson

Tony San

A signal decimating system decimates an initial data signal having an initial data rate R to a final data signal having a final data rate R&#x2033; in two stages, using a base decimation factor N and a decimation multiplier factor P. In the first stage, N FIR filters having coefficients corresponding to the final data rate R&#x2033; condition the initial data signal using the final data rate coefficients and thereafter decimate the initial data signal, as conditioned, by a base decimation factor of N to generate an intermediate data signal having an intermediate data rate R', where In the second stage, a sub-sampling unit includes a switch that sub-samples the intermediate data signal at a sub-sampling rate P to generate a final data signal having a final data rate R&#x2033;, where 

Dynamically re-configurable signal decimation system using a finite impulse response (FIR) filter

An electronic design automation system merges embedded logic analyzer technology with system level design and analysis technology. Embedded logic analyzers provide hardware to allow board-level signal capture and subsequent analysis of test devices programmed with a hardware design generated using electronic design automation. System level environments provide interactive tools for entering, modeling, simulating and analyzing multi-domain systems such as DSP designs. Typically, a user enters a system level design as a block diagram, including embedded logic analyzer blocks. The user inserts such blocks at nodes in the design where he or she wishes to capture signals to verify the design.

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San Jose, CA, United States of America

Maria D'Souza