Texas Instruments Corporation

Maria B Hipona

Henry M Darley

Donald Edward Steiss

Michael C Gill

Dale C Earl

Jim Dodrill

Paul C Wang

Dinh T Ngo

Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48) (50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

High speed numerical processor for performing a plurality of numeric

A processor (10) operable to calculate division and square root functions comprises a multiplier (48) having a multiplier array (116), a pipeline register (50), a correction generator (122), and a converter/rounder (52). The products generated by the multiplier array (116) are fed back to the multiplier (48) to avoid delays associated with the remainder of the multiplier circuitry. The correction generator (122) which performs a subtraction of the product output form the multiplier array (116) from a constant, is disposed between the multiplier array (116) and the converter/rounder (52). Hence, the subtraction necessry to compute the next estimate may be performed in parallel with other multiplications, further reducing the time necessary to perform the calculation. Compare circuitry (120) is operable to compare the final approximation with an operand to quickly determine the direction of rounding.

Floating point/integer processor with divide and square root functions

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Dallas, TX, United States of America

Maria B Hipona