Kabushiki Kaisha Toshiba

Mari Otsuka

Kenichi Otsuka

Kazumasa Tanida

Hideo Numata

Naoko Yamaguchi

Tsuyoshi Matsumura

Masahiro Sekiguchi

Hideaki Harakawa

Masayuki Dohi

Takashi Shirono

Satoshi Hongo

Kazuya Mori

Hiroyuki Kamijiyo

Tomonori Kitakura

According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.

Manufacturing method of semiconductor device, semiconductor substrate, and camera module

A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried, and a silicon nitride film formed on the wiring interlayer film of the uppermost layer wherein Si&#x2014;H concentration is smaller than N&#x2014;H concentration.

Semiconductor device and method of manufacturing the same

Disclosed are an apparatus and a method for manufacturing a semiconductor device. A Si wafer set within an L/UL chamber is transferred under the state of a high vacuum through a transfer chamber into a Ti chamber. The wafer is heated to at least 300&deg; C. within the Ti chamber by a heating mechanism arranged within the Ti chamber. Then, a TiSi,film is formed at a bottom portion of a contact hole by a plasma CVD method using an Ar gas supplied through a gas line as a carrier gas and a TiCl,gas supplied through another gas line as a source gas, Ti in the source gas being self-aligned with Si in the wafer. The wafer having the TiSi,film formed therein is transferred through the transfer chamber into a W chamber without being exposed to the air atmosphere. Within the W chamber, a W film is consecutively deposited by a selective CVD method on the TiSi,film. The particular technique makes it possible to form the TiSi,film of a high quality at a bottom portion of the contact hole even if the contact hole has a large aspect ratio.

Apparatus and method for manufacturing a semiconductor device having a multi-wiring layer structure

In a method of manufacturing a semiconductor device having a multilayer wiring structure, it has at least two underlying layers having different etching conditions. Firstly, the native oxide film formed on one of the underlying layers, or a barrier metal layer, is etched out under etching conditions suitable for the barrier metal layer. Then, the surface of the barrier metal layer is capped with a plugging material having etching conditions similar to or substantially the same as those of the other one of the underlying layers, or a lower wiring layer. Subsequently, the native oxide film and the etching by-product formed on the lower wiring layer are etched out under etching conditions suitable for the lower wiring layer. Thereafter, contact holes for the two underlying layers are buried with a conductive substance to establish electric connection with their respective upper conductive layers. With the above described steps, the entire manufacturing process is significantly simplified and the time required for burying the contact holes is greatly reduced without remarkably increasing the contact resistance between the barrier metal layer and the lower wiring layer and the respective buried conductive substances.

Method of manufacturing semiconductor device having a multilayer wiring

An inter-level insulation film is formed on a first-level interconnection layer and part of the inter-level insulation film which lies on the first-level interconnection layer is etched to form a contact hole. After a natural oxidation film formed on the surface of part of the first-level interconnection layer which is exposed in the contact hole is removed, the resultant structure is exposed to a gas atmosphere containing halogen to purify the surface of the inter-level insulation film. After this, a contact plug is deposited and formed on the first-level interconnection layer which is exposed in the contact hole by the selective CVD method to fill in the contact hole. A second-level interconnection layer is formed on the inter-level insulation film and the first-level and second-level interconnection layers are electrically connected to each other via the contact plug.

Contact plug forming method

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Oita, Japan

Mari Otsuka