Nec Corporation

Renesas Electronics Corporation

Mari Amano

Yoshihiro Hayashi

Munehiro Tada

Naoya Furutake

Makoto Ueki

Takahiro Onodera

Masayoshi Tagami

A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring.

Semiconductor device with dual damascene wirings

Method for manufacturing dual damascene wiring in semiconductor device

A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point metal film. The copper interconnection film is polycrystalline, and crystal grains occupying 40% or more of an area of a unit interconnection surface among crystal grains forming the polycrystal are oriented to (111) in a substrate thickness direction. The copper interconnection film has crystal conformity with the noble metal liner film. In a case where the high-melting-point metal film is formed of Ti and the noble metal liner film is a Ru film, the high-melting-point metal of Ti dissolves into Ru in a solid state to form the noble metal liner. Thus, a copper interconnection is formed with both of Cu diffusion barrier characteristics and Cu crystal conformity.

Semiconductor device and method of manufacturing the same

The present invention provides a semiconductor device which is capable of enhancing adhesion at an interface between a wire-protection film and copper, suppressing dispersion of copper at the interface to avoid electromigration and stress-inducing voids, and having a highly reliable wire. An interlayer insulating film, and a first etching-stopper film are formed on a semiconductor substrate on which a semiconductor device is fabricated. A first alloy-wire covered with a first barrier metal film is formed on the first etching-stopper film by a damascene process. The first alloy-wire is covered at an upper surface thereof with a first wire-protection film. The first wire-protection film covering an upper surface of the first alloy-wire contains at least one metal among metals contained in the first alloy-wire.

Semiconductor device and method of fabricating the same

A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400&#xb0; C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400&#xb0; C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented.

Semiconductor device

A multilayered wiring is formed in a prescribed area in an insulating film that is formed on a semiconductor substrate. Dual damascene wiring that is positioned on at least one layer of the multilayered wiring is composed of an alloy having copper as a principal component. The concentration of at least one metallic element contained in the alloy as an added component in vias of the dual damascene wiring is determined according to the differences in the width of the wiring of an upper layer where the vias are connected. Specifically, a larger wiring width in the upper layer corresponds to a higher concentration of at least one metallic element within the connected vias. Accordingly, increases in the resistance of the wiring are minimized, the incidence of stress-induced voids is reduced, and reliability can be improved.

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Tokyo, Japan

Mari Amano