Intel Corporation

Margareth E Marrugo

Niranjan L Cooray

Alaa R Alameldeen

Jayesh Gaur

Chinnakrishnan S Ballapuram

Manuel A Aguilar Arreola

Steven D Pudar

A cache memory data compression and decompression technique is described. A processor device includes a memory controller unit (MCU) coupled to a main memory and a cache memory. The MCU includes a cache memory data compression and decompression module that compresses data received from the main memory. The compressed data may then be stored in the cache memory. The cache memory data compression and decompression module may also decompress data that is stored in the cache memory. For example, in response to a cache hit for data requested by a processor, the compressed data in the cache memory may be decompressed and subsequently read or operated upon by the processor.

Growing community of inventors

El Dorado Hills, CA, United States of America

Margareth E Marrugo