Infineon Technologies Ag

Qimonda North America Corporation

Qimonda Ag

Infineon Technologies North America Corp.

Margaret Freebern

Wolfgang Hokenmaier

Kazimierz Szczypinski

Ralf Klein

Donald W Labrecque

Steffen Loeffler

An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory array. The second mode includes receiving multiplexed data signals and address signals on the first pads to access the memory array.

Integrated circuit including selectable address and data multiplexing mode

A memory includes an input pad for receiving an input signal and a first circuit. The first circuit is configured to receive a first signal in response to the input signal and receive a second signal and provide a third signal in response to at least one of the first signal and the second signal indicating a request to enter a deep power down mode. The memory includes a second circuit configured to provide a fourth signal indicating an entry to the deep power down mode in response to the third signal.

Memory including deep power down mode

A random access memory including multiple state machines and selection circuitry. The multiple state machines include a first state machine and a second state machine, and possibly more state machines. The first state machine is configured to provide first signals to control the random access memory and provide first command operations and the second state machine is configured to provide second signals to control the random access memory and provide second command operations. The selection circuitry selects one of the multiple state machines. The selection circuitry conducts the first signals to select the first state machine and provide the first command operations and the selection circuitry conducts the second signals to select the second state machine and provide the second command operations.

Random access memory including multiple state machines

A memory includes a row address latch. The row address latch includes a first stage configured to latch a row address for a memory read or write operation, and a second stage configured to latch a row address for a memory bank auto-refresh. The row address latch provides the row address from the first stage in response to an activate command and provides the row address from the second stage in response to a directed auto-refresh command.

Directed auto-refresh for a dynamic random access memory

A memory includes at least two memory banks, each memory bank including an array of memory cells including rows and columns. The memory includes a directed auto-refresh memory bank selection circuit configured to simultaneously select a first of the at least two memory banks for a read or write operation and a second of the at least two memory banks for a directed auto-refresh.

Memory having directed auto-refresh

A random access memory that includes an array of memory cells, a first circuit configured to receive an address to address memory cells in the array of memory cells, and a second circuit. The second circuit is configured to obtain control signals including an address strobe signal and gate the address strobe signal using other control signals to provide a gated address strobe signal and to control activation of a select line signal based on the gated address strobe signal.

Random access memory including selective activation of select line

A memory device includes: a memory array for storing data; data pads for supplying as an output of the memory device data retrieved from the memory array in a read operation; parallel read data paths each coupled between the memory array and the data pads, where the parallel read data paths include synchronous data paths operable in different modes of operation and an asynchronous data path; and a mode selector for selecting one of the parallel read data paths to supply data retrieved from the memory array to the data pads.

Parallel data path architecture

A memory comprises a column decoder and a circuit. The circuit is configured to receive a column address strobe signal, a column active signal, and a column addresses signal. The circuit is configured to pass the column addresses signal to the column decoder if the column address strobe signal and the column active signal are at a first logic level, and latch the column addresses signal and pass the latched column addresses signal to the column decoder if one of the column address strobe signal and the column active signal are at a second logic level different from the first logic level.

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Richmond, VT, United States of America

Margaret Freebern