International Business Machines Corporation

Margaret E Claffey-Cohen

James Peter Ward

Timothy J Louie

Alan F Neel, Ii

James Francis Webb

James Ronald Booth

Mark G Noll

James C Buchanan

Carl P Cole

Lynn M Oliver

James L Beck

Jose A Olive

Roberto V Perez

James P, Ward

Phat T Le

A timeout mechanism for a computer system is provided, comprising a clocked linear feedback shift register and a programmable comparing mechanism. The linear feedback shift register comprises a series of latches serially connected to each other, and is responsive to a received interrupt signal to (i) incrementally count sequentially in the presence of the interrupt signal to provide a distinct binary vector array at the outputs of the latches for each count in the sequence and (ii) reset to a particular binary vector array in the absence of the interrupt signal. The comparing mechanism outputs a timeout command in response to the linear feedback shift register reaching a predetermined count and outputting a corresponding predetermined binary vector array at the output of the latches. The timeout mechanism uses a minimal amount of combinatorial logic, while permitting the issuance of a timeout command after the detection of an interrupt signal after any multiple of clock cycles.

Programmable linear feedback shift register timeout mechanism

A parallel port interface for utilization between a first device and a second device designated by a user for transmitting a digital signal from the device to the second device. The parallel port interface includes a switchable driver circuit for transmitting the digital signal, which includes a first circuit for emulating an open collector circuit and a second circuit for emulating a totem pole circuit. The switchable driver circuit is controlled by a logic control circuit that automatically selects either the first circuit or the second circuit for transmitting the digital signal in response to the digital signal and a designation of the second device.

Method and apparatus for controlling parallel port drivers in a data

A parallel interface connects a data processor and a printer so that each may transmit information to the other or receive information from the other. The transmitted information from the data processor can be data or status signals. The data or status signals are transmitted over the same eight information lines between the data processor and the printer with a predetermined signal being sent over another line from the data processor to the printer prior to transmission over the eight lines to identify whether the transmitted information is data or status signals. The printer sends status signals to the data processor over the same eight information lines after sending a predetermined signal to the data processor over a further line that it is going to transmit.

Bi-directional parallel printer interface

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Jupiter, FL, United States of America

Margaret E Claffey-Cohen