Nxp USA, Inc.

Freescale Semiconductor,inc.

Other

Margaret A Szymanowski

Fernando A Santos

Sarmad K Musa

Shun Meen Kuo

Paul Richard Hart

Mahesh K Shah

Xin Fu

Elie A Maalouf

Xavier Hue

Seungkee Min

Joseph Staudinger

Jeffrey Kevin Jones

Ramanujam Srinidhi Embar

Xiaowei Ren

Wayne R Burger

Michele Lynn Miera

Colin Kerr

Mark A Bennett

Michael E Watts

Robert A Pryor

Roy McLaren

Jerry Lynn White

Monte Gene Miller

L Mali Mahalingam

Maruf Ahmed

Henry Andre Christange

Chun-Wei Chang

Mohd Salimin Sahludin

Namsik Ryu

Kimberly J Foxx

A multiple-path amplifier (e.g., a Doherty amplifier) includes first and second transistors (e.g., main and peaking transistors) with first and second output terminals, respectively, all of which is integrally-formed with a semiconductor die. A signal path through the second transistor extends in a direction from a control terminal of the second transistor to the second output terminal, where the second output terminal corresponds to or is closely electrically coupled to a combining node. The amplifier also includes an integrated phase delay circuit that is configured to apply an overall phase delay (e.g., 90 degrees) to a signal carried between the first and second output terminals. The integrated phase delay circuit includes delay circuit wirebonds coupled between the first and second output terminals, and the delay circuit wirebonds extend in a third direction that is angularly offset from (e.g., perpendicular to) the second direction.

Integrated multiple-path power amplifier

Embodiments of a digital step attenuator are disclosed. In an embodiment, a digital step attenuator includes a radio frequency (RF) input, an RF output, an attenuation circuit connected between the RF input and the RF output, a shunt switching circuit connected to the attenuator circuit, and a bypass switching circuit connected between the RF input and the RF output. The bypass switching circuit includes a first bypass transistor, and a second bypass transistor, wherein the first bypass transistor and the second bypass transistor are series connected to each other between the RF input and the RF output, and a bypass shunt transistor connected between the first bypass transistor and the second bypass transistor.

Digital step attenuator and method for operating a digital step attenuator

A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier.

Integrally-formed multiple-path power amplifier with on-die combining node structure

A multiple-path (e.g., Doherty) amplifier includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, first and second amplifiers (e.g., main and peaking amplifiers, or vice versa) integrally formed with the semiconductor die, and a shunt circuit electrically connected between an output of the first amplifier and a ground reference node. Inputs of the first and second amplifier are electrically coupled to the RF signal input terminal, and outputs of the first and second amplifier are electrically coupled to the combining node structure. The shunt circuit includes a shunt inductance and a shunt capacitance coupled in series between the output of the first amplifier and the ground reference node, and the shunt capacitance has a first terminal coupled to the shunt inductance, and a second terminal coupled to the ground reference node.

Power amplifier integrated circuit with integrated shunt-l circuit at amplifier output

A power amplifier includes a semiconductor die, and an amplifier and bias circuit integrally formed with the semiconductor die. The die has opposed first and second sides, and a device bisection line extends between the first and second sides. The bias circuit includes a multi-point input terminal with first and second terminals that are electrically connected through a conductive path that extends across the device bisection line, and one or more bias circuit components connected between the multi-point input terminal and the amplifier. The amplifier may include a field effect transistor (FET) with gate and drain terminals, and the bias circuit component(s) are electrically connected between the multi-point input terminal and the gate terminal. In addition or alternatively, the bias circuit component(s) are electrically connected between a multi-point input terminal and the drain terminal. The one or more components may include a resistor-divider circuit.

Power amplifier with integrated bias circuit having multi-point input

A multiple-stage amplifier includes a driver stage transistor characterized by a first power density, and a final stage transistor characterized by a second power density that is larger than the first power density. A first drain bias circuit is coupled to a first drain terminal of the driver stage transistor, and is configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to a second drain terminal of the final stage transistor, and is configured to provide a second drain bias voltage to the second drain terminal, where the second drain bias voltage equals the first drain bias voltage. An interstage impedance matching circuit is coupled between the first drain terminal and a gate terminal of the final stage transistor. The multiple-stage amplifier may be included in a Doherty power amplifier, a transceiver, and/or a transceiver array.

Multiple-stage power amplifiers and amplifier arrays configured to operate using the same output bias voltage

A Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and first and second peaking amplifier dies. The RF signal splitter divides an input RF signal into first, second, and third input RF signals, and conveys the input RF signals to splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier dies each include one or more additional power transistors configured to amplify, along first and second peaking signal paths, the second and third input RF signals to produce amplified second and third RF signals. The dies are coupled to the substrate so that the RF signal paths through the carrier and one or more of the peaking amplifier dies extend in substantially different (e.g., orthogonal) directions.

Multiple-path RF amplifiers with angularly offset signal path directions, and methods of manufacture thereof

A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die. The multiple-path amplifier also may include an integrated phase shifter/impedance inverter coupled between the outputs of the first and second transistors, and which is configured to impart a 90-degree phase delay between intrinsic drains of the first and second transistors.

A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.

Semiconductor package having an isolation wall to reduce electromagnetic coupling

An amplifier device includes an input terminal, an output terminal, a first transistor having a control terminal and first and second current-carrying terminals, and a class-J circuit coupled between the second current-carrying terminal of the first transistor and the output terminal and configured to harmonically terminate the first transistor. The class-J circuit may include a first resonator, characterized by a first resonant frequency substantially equal to a second harmonic frequency. The first resonator may be coupled between the second current-carrying terminal and a voltage reference. A shunt inductor that is distinct from the first resonator may be coupled between the second current-carrying terminal and the voltage reference.

Amplifier device with harmonic termination circuit

An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions.

A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.

Semiconductor packages having wire bond wall to reduce coupling

An amplifier includes first, second, and third inputs to receive an RF signal, first and second amplifiers, and an input phase adjustment circuit coupling the first, second, and third inputs to the first and second amplifiers, the input phase adjustment circuit having first and second outputs coupled to the first and second amplifiers, respectively. The input phase adjustment circuit includes a pair of inputs, where the pair of inputs includes the first and second inputs, for the first output and a pair of phase adjustment paths coupling the pair of inputs to the first output, respectively. The pair of phase adjustment paths are configured to adjust a phase of the RF signal differently for the first output.

Growing community of inventors

Austin, TX, United States of America

Margaret A Szymanowski