Akademia Gorniczo-hutnicza Im. Stanislawa Staszica

Akademia Gorniczo-hutnicza Im. Stanislawa Staszica, Al.

Akademia Gornicz0-hutnicza Im Stanislawa Staszica

Akademia Gorniczo-hutnicza Im. Stanislawa Staszica W Krakowie

Marek Miskowicz

Dariusz Koscielnik

Andrzej Szaflarski

Katarzyna Heryan

Wojciech Reklewski

Marek Kisiel-Dorohinicki

Konrad Jurasz

Jakub Szyduczynski

A method and apparatus for conversion of a time interval to a digital word, the time interval being mapped to a difference of a length of a reference time and a length of a signal time. Reference time is generated from an instant when the beginning of the time interval is detected, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module. The generation of the reference time and the signal time is terminated at the same instant. In the apparatus, bottom plates of capacitors of the set of capacitors are connected to a ground of the circuit, and top plates of these capacitors are connected, respectively, to moving contacts of change-over switches. First, second, and third stationary contacts are connected to the signal rail, the ground of the circuit, and to the reference rail.

Method and apparatus for conversion of value of analog signal to compressed digital word

A method for indirect conversion of a voltage value to a digital word consisting in sampling an input voltage through a parallel connection of a sampling capacitor to a source of the input voltage, and next in mapping a sample value of the input voltage to a time interval, and in assignment of a corresponding value of n-bit output digital word by the use a control module characterized in that the time interval is mapped to a difference of a length of a reference time and a length of a signal time, while the reference time is generated from an instant when the beginning of the time interval is detected by the use the control module, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module, whereas generation of the reference time and the signal time is terminated at the same instant.

Method and apparatus for indirect conversion of voltage value to digital word

Method for encoding analog signal into time intervals wherein a generation of time intervals using a time encoding machine. A signal of a constant value is held during a generated time interval on a time encoding machine input by the use of a sample-and-hold circuit, while the constant value of the signal held during the generated time interval represents an instantaneous value of the analog signal at the end of a generation of a previous time interval. Apparatus for encoding analog signal into time intervals comprising a time encoding machine, and a sample-and-hold circuit. The signal is provided to an input of the sample-and-hold circuit, whose output is connected to an output of the time encoding machine. The output of the time encoding machine is connected to an output of the apparatus, and to a control input of the sample-and-hold circuit.

Method and apparatus for encoding analog signal into time intervals

A method and apparatus for conversion of a time interval to a digital word, the time interval being mapped to a difference of a length of a reference time and a length of a signal time. Reference time is generated from an instant when the beginning of the time interval is detected, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module. The generation of the reference time and the signal time is terminated at the same instant. In the apparatus, bottom plates of capacitors of the set of capacitors are connected to a ground of the circuit, and top plates of these capacitors are connected, respectively, to moving contacts of change-over switches First, second, and third stationary contacts are connected to the signal rail, the ground of the circuit, and to the reference rail.

Method and apparatus for conversion of time interval to digital word using successive approximation scheme

Method of controlling the access of devices to the communication media in distributed networks of CSMA (Carrier Sense Multiple Access) type is characterized by that each time before the packet transmission attempt, if the communication medium is detected to be idle, the prespecified fixed time interval equal to the minimum interpacket space is timed out during which the random numbers of time slots defining the order of media access are selected from the fixed number of slots of equal width using the pseudorandom number generator in every node where the probability of a selection of a particular slot is geometric with a characteristic parameter defined as the ratio of the probability of a selection of a given slot to the probability of a selection of the next slot, which changes from zero to one as a discrete function of the state of the node's counter, and after that the time interval of random delay corresponding to the selected random is assigned. After the minimum interpacket space the phase of known sequential priority access is started and subsequently, the random delay assigned previously is timed out and at the same time the state of the communication medium is sensed again, and if the communication medium is still sensed idle, it is made available to the node with the lowest number of the slot randomly selected. After completing a given packet reception, the states of the counters in all the nodes in a given network segment are increased by the increment defining the number of expected packets that will be generated in a result of the reception of the transmitted packet reduced by one, and next, the cycle is repeated. During the data packet transmission the collisions are detected optionally in the communication medium by the collision detectors, and next, the states of the counters are changed in the nodes with the use of the corresponding control signals obtained from the collision detectors, and in case the communication medium is detected to be idle after the time equal to the sum of the minimum interpacket space and the time delay defined by the prespecified fixed maximum number of slots, the states of the counters in all the nodes in a given network segment are decreased by one with the use of the control signals obtained from the communication medium state detectors.

Method of controlling access of devices to communication medium in distributed networks

The method includes the accumulation of electric charge in the sampling capacitor (C) by parallel connection of the sampling capacitor (C) to the source of converted voltage (U) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). After detection of the beginning of the next trigger signal (P), the charge is accumulated in the additional sampling capacitor (C), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. The apparatus includes an array of redistribution (A), the section of the sampling capacitor (A), the control module (CM), two comparators (Kand K) and the current source (J) connected in a known way.

Method and apparatus for clockless conversion of instantaneous voltage value to digital word

The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (C, . . . , C) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((C, . . . , C)) in the order of decreasing capacitances starting from the capacitor (C) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (C) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K) and (K) without the use of a clock while the value one is assigned to these bits (b, . . . , b) in the digital output word that correspond to the capacitors (C, . . . , C) on which the reference voltage (U) of a desired value has been obtained, and the value zero is assigned to the other bits.

Method and apparatus for conversion of time interval to digital word

The solution according to the invention consisting in conversion of a voltage value to a digital word of a number of bits equal to n is characterized in that the converted voltage value is first mapped to a portion of electric charge accumulated in the sampling capacitor (C-) during the active state of the signal on the trigger input (InS) and the accumulated charge portion is next successively redistributed by the use of the current source (I) in the array (A) of binary-scaled capacitors (C, . . . , C) in the order of decreasing capacitances starting from the capacitor (C) having the highest capacitance value in the array (A). The process of charge redistribution is controlled by the control module (CM) on the basis of the output signals of the comparators (K) and (K) without the use of a clock while the value one is assigned to these bits (b, . . . , b) in the digital output word that correspond to the capacitors (C, . . . , C) on which the reference voltage (U) of a desired value has been obtained, and the value zero is assigned to the other bits.

Method and apparatus for conversion of voltage value to digital word

The solution according to the invention consisting in conversion of a portion of electric charge to a digital word of a number of bits equal to n by the use of successive redistribution of charge in the array (A) of binary-scaled capacitors (C, . . . , C) is characterized in that charge is first accumulated during the active state of the external gate signal on the gate signal input (InG) in the capacitors (C, . . . , C) in the order of decreasing capacitances starting from the capacitor (C) having the highest capacitance value in the array, and when the active state of the gate signal is terminated, the charge accumulated in the capacitor (C) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values. The process of charge transfer is controlled by the control module (CM) on the basis of the output signals of the comparators (K) and (K) without the use of a clock while the value one is assigned to these bits (b, . . . , b) in the digital output word that correspond to the capacitors (C, . . . , C) on which the reference voltage (U) of a desired value has been obtained, and the value zero is assigned to the other bits.

Method and apparatus for conversion of portion of electric charge to digital word

Method and apparatus for mapping the converted voltage value by electric charge value proportional to the converted voltage value and in accumulation of charge in the sampling capacitor until the voltage on this capacitor is equal to the converted voltage. Furthermore, realization of the process of that electric charge redistribution in the array of redistribution by changes of states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. As soon as accumulation of electric charge in the sampling capacitor is terminated, electric charge is accumulated in the additional sampling capacitor then the process of that electric charge redistribution is realized and relevant values are assigned to bits of the digital word. When a trigger signal is detected, next cycle begins and electric charge is accumulated in the sampling capacitor.

Method and apparatus for clockless conversion of voltage value to digital word

A conversion module contains an asynchronous analog-to-digital converter (AADC) with the output signal generated at irregular time intervals, whose output is connected to the input of the buffer memory module (BUF), and the output of the buffer memory module (BUF) is connected through the internal bus (BUS) simultaneously to the source address module (SADR), to the configuration registers module (REG), to the control module of the interface (CM), which the reference generator (RG) is connected to, and to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and moreover the control inputs/outputs () of the control module (CM) are connected respectively to the asynchronous analog-to-digital converter (AADC), to the buffer memory module (BUF), to the source address module (SADR), to the configuration registers module (REG), to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and to the clock control module (SCM), and on the other hand, the transmitter/receiver module (SDM) output is connected through the controller (SDD) to the data line (SDA) of the I2C bus whose clock line (SCL) is connected through the other controller (SCD) to the clock control module (SCD) output, and what is more the write control output () of the asynchronous analog-to-digital converter (AADC) is connected to the write control input () of the buffer memory module (BUF).

Interface for communication between sensing devices and I2C bus

Method and apparatus for accumulation of electric charge delivered to the charge input (InQ) in the sampling capacitor (C) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). Method is characterized in that after detection of the beginning of the next gate signal (G), the charge is accumulated in the additional sampling capacitor (C), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent gate signal (G) is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor (C) again.

Method and apparatus for clockless conversion of portion of electric charge to digital word

Method and apparatus for detecting the beginning and end of a time interval using the control module and in mapping this time interval to a portion of electric charge proportional to this time interval and accumulated in the sampling capacitor and then realizing the process of charge redistribution in the array of redistribution by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. After detection of the beginning of the next time interval, the charge is accumulated in the additional sampling capacitor and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent time interval is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor again.

Method and apparatus for clockless conversion of time interval to digital word

Analog to digital conversion characterized in that the square wave (z(t)) obtained as a result of modulation in an asynchronous Sigma-Delta modulator (ASDM) is subjected to conversion by counting the periods (T) of the reference clock (RG) during subsequent pulses of the square wave by means of the counting module (CTM), and then each word obtained representing the number of periods of the reference clock counted during each given pulse of the square wave is recorded and stored in the intermediate buffer (TBUF). The duration of the serial transmission of the digital word obtained as a result of counting the periods of the reference clock during previous pulse of the square wave is simultaneously controlled by the control module (CM), and as soon as this transmission is completed, the content of the intermediate buffer (TBUF) is transferred to the transmitting buffer (TDR) of the apparatus.

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Cracow, Poland

Marek Miskowicz