Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Marek J Marasch

Mark Franklin Turner

Jeff S Brown

Jay Daugherty

Jeffrey Scott Brown

Jay D Harker

Carol A Anderson

John Gatt

A method for enhancing signal integrity in an interface between a source device and at least one destination device includes: analyzing two or more consecutive data patterns intended to be conveyed by the interface to determine whether data transitions corresponding to the data patterns are likely to introduce coupling noise and/or simultaneous switching output (SSO) effects on the interface; generating a modified data pattern for transmission by the interface, the modified data pattern reducing coupling noise and/or SSO effects on the interface compared to an original data pattern intended to be conveyed by the interface; and transmitting the modified data pattern and information regarding a manner in which the original data pattern was modified to the destination device to thereby reduce coupling noise and/or SSO effects on the interface.

Parallel interface pattern modification for addressing signal integrity concerns

A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths.

System and method for decreasing signal integrity noise by using varying drive strengths based on likelihood of signals becoming victims

Disclosed is a diode clamping circuit that is used in an I/O buffer to suppress noise. Diode-connected CMOS transistors or PN junction transistors are utilized, which are native to the CMOS process. Switching circuitry is also disclosed to isolate the diodes and prevent current drain in the circuit. Switching circuitry is also used to switch between two different power supply voltages.

Overshoot suppression for input/output buffers

A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.

Method of generating a restricted inline resistive fault pattern and a test pattern generator

A method of testing a tristate element by applying a given value to the tristate, applying an opposite value to a keeper element connected at an output of the tristate, capturing a first value at a downstream position of the tristate, evaluating a second value at the output of the tristate using the first value, comparing the second value to the opposite value, and producing a failure code for the tristate when the second value is not equal to the opposite value. Then, applying the opposite value to the tristate, applying the given value to the keeper element, capturing the first value, evaluating the second value using the first value, comparing the second value to the given value, and producing a failure code for the tristate when the second value is not equal to the given value. A passing code for the tristate is produced when a failure code has not been produced.

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Longmont, CO, United States of America

Marek J Marasch