International Business Machines Corporation

Marek Andrzej Orlowski

David L Questad

Jeffrey Allen Zitz

Sushumna Iruvanti

Thomas Anthony Wassick

Shidong Li

Krishna R Tunga

Tuhin Sinha

Paul Robert Walling

Randall Jason Werner

David Brian Stone

Mark C H Lamorey

Douglas Oliver Powell

Jean Audet

Anson Jay Call

Jason Lee Frankel

Franklin M Baez

Erwin B Cohen

Kevin Grosselfinger

Roxan Lemire

Deana Cosmadelis

Alain Ayotte

Gilles Poitras

A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.

Automated generation of surface-mount package design

A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

Test cell for laminate and method

A computer-implemented method provides an elastic modulus map of a chip carrier of a flip chip package. Design data including dielectric and conductive design elements of each of vertically aligned sub-areas of each of the layers of the chip carrier are modeled as springs to provide the elastic modulus map. Determining the elastic modulus of the sub-areas of the chip carrier identifies probable mechanical failure sites during chip-join and cools down of the flip chip package. Modifying a footprint of solder bumps to the chip carrier reduces stresses applied to the identified probable mechanical failure sites. Modifying the chip carrier design to reduce a stiffness of sub-areas associated with identified probable mechanical failure sites also reduces stresses from chip-join and cool-down.

Elastic modulus mapping of a chip carrier in a flip chip package

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Fishkill, NY, United States of America

Marek Andrzej Orlowski