Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Marefusa Kurumada

Toshio Terano

Yoshinobu Yamagami

Satoshi Ishikura

Hironori Akamatsu

Hiroaki Okuyama

Katsuji Satomi

Toshikazu Suzuki

Yutaka Terada

Masanori Shirahama

Kenji Motomochi

Kazuhiro Takemura

Tomoyuki Aihara

A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.

Semiconductor memory device

A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.

A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced.

A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.

The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macrosAandAincludes a memory cell arrayA-connected to word lines WLto WLand bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line BLAand outputs defect information to a redundant signal line RA. The redundant memory macroA includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

Semiconductor integrated circuit including memory macro

In data read, a single read global bit line is shared with a plurality of local bit lines.

Semiconductor memory device realizing high-speed access

The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros includes a memory cell array connected to word lines and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line and outputs defect information to a redundant signal line. The redundant memory macro includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

A semiconductor memory device is provided which has a unit by which a fail bit map can be checked instantaneously over the entire address space. The semiconductor memory device is provided with a data logic forcefully controlling circuitwhich forcefully controls the logic of write data into memory cells selected by using a specified address signal or of read data, a specified row forcefully controlling circuitwhich forcefully makes the control of memory cells selected according to specified row addresses the control exercised during operation different from normal operation, or a specified column forcefully controlling circuitwhich forcefully makes the control of memory cells selected according to specified column addresses the control exercised during operation different from normal operation. This forced fail operation mode is selectable aside from normal operation mode.

Semiconductor memory device having forced fail function of forcing a memory cell at a specific address to fail and method for testing same

In a multiport memory, in the event of simultaneous read/write operation for the same row address, a read word line pulse signal, output from a read control circuit for memory access based on an externally supplied read enable signal and read clock signal, is input into a write control circuit, to delay start of the write operation until termination of the read operation. This can delay the timing of activating a write word line by a write row decoder behind the timing of activating a read word line by a read row decoder, to allow the read operation first followed by the write operation. Therefore, since the read operation is performed while the write word line being kept closed, the trouble of data processing becoming uncertain due to addition of the load of a write bit line to a read bit line can be prevented.

Semiconductor memory

A semiconductor memory device capable of enhancing a production yield is provided. A dummy control circuit activates a first dummy column including a plurality of dummy cells placed at a position close to a row decoder in a row direction and a second dummy column including a plurality of dummy cells placed at a position farthest from the row decoder in a row direction with a plurality of memory cells interposed between the first dummy column and the second dummy column, through first and second dummy word lines. A dummy column selector selects either one of a signal on a first dummy bit line connected to the first dummy column and a signal on a second dummy bit line connected to the second dummy column, and outputs the selected signal to an amplifier control circuit. The amplifier control circuit generates an amplifier startup signal with respect to an amplifier circuit based on a signal from the dummy column selector.

Growing community of inventors

Kyoto, Japan

Marefusa Kurumada