United Microelectronics Corp.

Marcus Yang

Yuan-Li Tsai

Ralph Chen

Ching-Chun Huang

Sheng-Hsiung Yang

Ching-Chun Hwang

Heng-Chun Kao

A method is provided to fabricate a LCOS back plane structure. The present invention utilized a HV device such as HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) and a HV capacitor layer are applied to the substrate. Furthermore, the HV capacitor layer has a higher dielectric layer and coupling ratio to sustain the higher operating voltage, such that the operating capacitance can be raised. Moreover, the HV CMOS transistor is combined with a mirror layer which has a higher reflective property, such that the LCOS back-plate structure has the better contrast and chrominance output in per area unit, when the operating voltage range is increased.

Method of fabrication LCOS structure

The method for forming high voltage device combined with a mixed mode process use an un-doped polysilicon layer instead of the conventional polysilicon layer. In the high resistance area, the ion implant is not used until the source region and the drain region are formed. A resistor is formed by etching oxide-nitride-oxide layer and performing ion implant process by using BF radical to the un-doped polysilicon layer to control the resistance. Then multitudes of contact are formed, wherein the high dosage of BF implant would reduce resistance between contacts and resistor.

Method for forming high resistance resistor with integrated high voltage device process

Growing community of inventors

Chang-Hua, Taiwan

Marcus Yang