Cadence Design Systems, Inc.

Marcus Vinicius Da Mata Gomes

Lawrence Loh

Antonio Celso Caldeira, Jr

Fabiano Cruz Peixoto

Rajeev Kumar Ranjan

Andrea Iabrudi Tavares

Xiaoyang Sun

Various mechanisms and approaches identify a first electronic design component at least by traversing at least a portion of the electronic design and generate a representation of the electronic design by interconnecting one or more duplicated electronic design components within the representation. The first electronic design component may include a destination electronic design component with a backward traversal of the electronic design. One or more fan-in electronic design components may be duplicated into the one or more duplicated electronic design components. One or more CDC effect models are automatically injected into the representation by adding the one or more CDC effect models along one or more paths in the representation. Proof results are generated at least via proving or disproving one or more checkers for the electronic design by verifying or simulating the representation with the one or more CDC effect models that are automatically injected into the representation.

Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths

An improved approach is provided to implement equivalency checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis. Instead, the two designs are checked to see if they are equivalent on the transaction-level. This approach abstracts the timing delays between the two designs, which allows verification of data transportation and transformation between the designs.

Method and system to perform equivalency checks

An improved approach is provided to implement performance checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis, where the two designs are checked to see if they are equivalent on the transaction-level. Thereafter, the outputs for the transactions are analyzed relative to delay time periods, which allows verification and identification of possible performance issues and differences between the two designs.

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San Jose, CA, United States of America

Marcus Vinicius Da Mata Gomes