Rambus Inc.

Cadence Design Systems, Inc.

Movellus Circuits Inc.

Semtech Canada Corporation

Rambus Canada Inc.

Marcus Van Ierssel

Nanyan Wang

David J Cassan

Kenneth Colin Dyer

Mehrdad Ramezani

Christopher D Holdenried

Ravi Shivnaraine

Sang-Wook Paul Park

Dominic DiClemente

Mohammad Sadegh Jalali

Chris Holdenried

Mohamed Abdalla

Afshin Rezayee

Jeffrey Alan Fredenburg

Xiao Wu

Saman Sadr

David Moore

Saif Elam

Brian Che Yuen Lam

Vikram Karvat

Prabhnoor Singh Kainth

George Chung Fai Ng

An integrated circuit (IC) chip includes transmit circuitry including multiple transmitters to launch parallel data in response to a transmit clock signal. The transmit clock signal is based on a reference clock signal. Receiver circuitry includes multiple receivers to receive the parallel data in response to a receive clock signal. The receive clock signal is based on the reference clock signal. Bus circuitry includes multiple data paths arranged in parallel between the transmit circuitry and the receiver circuitry. Each data path is coupled between a given one of the multiple transmitters and a given one of the multiple receivers. A first data path of the multiple data paths includes a delay circuit to dynamically delay first data of the parallel data propagating along the first data path by a first delay that is based on a channel delay exhibited by a second data path of the multiple data paths.

Self-aligning interconnect for a digital system

A clock generator system includes a first clock generator circuit to generate a first clock output signal having a first clock output frequency that is within a first bounded range of frequencies. The first clock generator circuit, during a transition mode, exhibits a first ramping of the first clock output signal from the first clock output frequency towards a target frequency. The system includes a second clock generator circuit to generate a second clock output signal having a second clock output frequency that is within a second bounded range of frequencies. The second clock generator circuit, during the transition mode, exhibits a second ramping of the second clock output signal from a second frequency towards the target frequency. A controller coupled to the first clock generator circuit and the second clock generator circuit selectively passes one of the first clock output signal or the second clock output signal as a system clock output signal. The controller, upon a desired change from a first system clock output frequency to the target frequency, switches from the first clock output signal to the second clock output signal at a dynamically-determined frequency crossover threshold.

Clock generator system with dynamic frequency crossover

A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.

Live offset cancellation of the decision feedback equalization data slicers

An integrated circuit that includes a feedback loop to adapt receiver parameters. The feedback loop includes a receiver to sample a signal and produce a sampled signal sequence. The feedback loop also includes a first pattern counter to detect and count occurrences of a first pattern in the sampled signal sequence, and a second pattern counter to detect and count occurrences of a second pattern in the sampled signal sequence. Control circuitry coupled to the receiver adapts a parameter value of the receiver to minimize a difference between a first ratio and a second ratio. The first ratio is a target ratio. The second ratio is between a first counted number of occurrences of the first pattern in the sampled signal sequence and a second counted number of occurrences of the second pattern in the sample signal sequence.

Pattern detection based parameter adaptation

A clock-and-data recovery circuit for serial receiver includes a jitter meter and an adaptive loop gain adjustment circuitry. The clock-recovery circuitry phase aligns a clock signal to the incoming data. A jitter meter provides a measure of jitter, while adaptation circuitry uses the measure to adjust the clock-recovery circuitry in a manner that reduces clock jitter. The jitter measure can be a ratio of errors associated with different inter-symbol slew rates.

Methods and circuits for reducing clock jitter

A phase-locked loop (PLL) includes a phase-frequency detector that compares a reference signal to a feedback signal. The difference in phase between the reference signal and the feedback signal is encoded as digital pulses on one or more outputs of the phase-frequency detector. The digital output pulses from the phase-frequency detector are duplicated and delayed multiple times in a non-overlapping manner before being input to the loop filter or voltage controlled oscillator (VCO) of the PLL.

Phase-locked loop with phase information multiplication

A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.

Matched digital-to-analog converters

Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.

Offset calibration for successive approximation register analog to digital converter

A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

Baud-rate clock recovery lock point control

A receiver samples an analog, multi-level, pulse-amplitude-modulated signal using a clock-and-data recovery circuit (CDR) that samples the signal against adaptively calibrated symbol-decision thresholds in time with a clock signal that is phased aligned with and locked to the signal. The CDR can erroneously align the clock signal to inter-symbol edges of the signal, a condition called 'edge lock,' rather than on the symbols themselves. A transition-type detector senses the edge-lock condition and unlocks the CDR, which can then realign the clock signal, this time on the symbols rather than the inter-symbol edges. The receiver can also respond to the edge-lock condition by kick-starting a shift of symbol-decision threshold that helps the CDR settle more quickly on correct symbol-decision thresholds.

Circuits and methods for detecting and unlocking edge-phase lock

A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0&#xb0;-90&#xb0;, 90&#xb0;-180&#xb0;, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.

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Marcus Van Ierssel