Infineon Technologies Ag

Infineon Technologies Austria Ag

Marcus Nuebling

Jens Barrenscheen

Tommaso Bacigalupo

Marco Bachhuber

Michael Krug

Laurent Beaurenaut

Markus Zannoth

Jaafar Mejri

Markus Winkler

Carmelo Giunta

Christoph Bauer

Christian Novak

Andreas Peter Meiser

Uwe Wahl

Bernhard Strzalkowski

Alexander Mayer

Tomas Manuel Reiter

Peter Kanschat

Benno Koeppl

Steffen Thiele

Jens-Peer Stengl

Werner Roessler

Tom Roewe

Mathias Racki

Matthias Weinmann

Bernard Strzalkowski

Heiko Gutzki

Benedikt Hanelt

Peter Weiß

Peter Weiss

This disclosure is directed to a driver circuit configured to control a power switch. The driver circuit may comprise an output pin, wherein the driver circuit is configured to deliver drive signals from the output pin to the power switch to control turn ON of the power switch; a multi-function pin; and a state machine configured to define operation of the driver circuit using the multi-function pin, wherein the state machine is configured to select among a soft turn OFF mode, a clamping mode, and an in-line characterization mode.

Driver circuit with a multi-function pin used for in-line characterization of a power switch

This disclosure describes a driver circuit configured to control a gate injection transistor (GIT). The driver circuit is configured to output a control current to a gate of the GIT, detect a voltage at the gate of the GIT, and determine a load current through the GIT based on the voltage detected at the gate of the GIT. The voltage at the gate of the GIT may be dependent on both the load current and the control current.

Techniques and driver circuits configured to monitor load current through a gate injection transistor (GIT)

Circuits, devices and systems that include a low voltage test for common mode transient immunity (CMTI). The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common mode transient rejection, the first signal path should be the same as the second signal path. Differences in the resistance, inductance, and capacitance between the two signal paths may result in common mode noise being measured as a differential signal at the output terminals. Devices according to the techniques of this disclosure are configured to enter a test mode to conduct a low voltage test that outputs a measurement of CMTI at any phase of production or field use.

Common mode evaluation in a differential galvanic isolation signal transmission circuit

A system including circuitry to communicate data across an isolation barrier of a switch driver circuit. For switch driver circuits with galvanic isolation, the circuitry of this disclosure uses the unavoidable common mode voltages caused by the coupling capacitances of the data transfer circuit to evaluate the common mode voltage characteristics, such as the slew rate of a switching event. The switch driver circuit of this disclosure may include a common mode voltage detector to detect and measure features of the unavoidable common mode voltage during a switching event, such as voltage amplitude and slew rate. The common mode voltage detector may couple to a communication interface that provides the common mode voltage information to a controller for the switch driver circuit. In some examples, based on the received information, the controller may adjust the operation of the switching circuit.

Common mode evaluation

Circuitry to automatically compensate a differential output oscillator circuit for common mode disturbances that may affect the oscillator output. For any differential oscillator the common mode voltage excursion may reduce the oscillator output, which in some examples may negatively affect the circuitry receiving the oscillator output. The addition of feedback circuitry with an automatic gain control, e.g., to regulate the differential output voltage, may further reduce the gain of the oscillator in the presence of common mode voltage. In contrast, the feedback circuitry of the oscillator circuit of this disclosure may include gain control circuitry to increase an output voltage amplitude at the differential output terminals for a duration of the common mode disturbance.

Low current oscillator structure with common mode transient noise cancelation

A device for controlling a current controlled switching element includes an output node, a current driver circuit, and detection circuitry. The output node is configured to electrically couple to a control node of the current controlled switching element. The current controlled switching element is configured to change from operating in an off-state to operating in an on-state when a charge supplied to the control node causes a voltage at the control node to be greater than an activation threshold. The current driver circuit configured to output an activation current to the output node in response to a switching signal indicating to change from operating the current controlled switching element from the off-state to the on-state. The detection circuitry is configured to detect, based on the voltage at the control node, when a switching event has occurred while the current driver circuit outputs the activation current.

Gate driver circuit for current controlled switching element

An example circuit includes a coil structure located on at least a first layer of an integrated circuit (IC); and a circuit component comprising conduction paths. The conduction paths are located on one or more layers separate from the first layer and the first layer and the one or more layers form parallel planes. The conduction paths of the circuit component are oriented to avoid eddy currents in the conduction paths caused by an electric current through the coil structure and form a patterned shield. At least some of the conduction paths define an area, and the coil structure is located within the defined area.

Active under shielding for coils and transformers

A drive circuit configured to apply a slew rate controlled drive signal to the control terminal of a power transistor. The drive circuit may be part of a system that includes one or more sub-circuits in which each sub-circuit includes a regulation loop, a matched replica of the power transistor and regulated voltage node. The voltage reference voltage for each sub-circuit connects to the control terminal of the power switch through a buffer circuit to apply a sequence of voltages to the control terminal of the power switch. A switching controller circuit may manage the operation of the one or more sub-circuits so that the drive circuit may output a precisely controlled voltage profile to the control terminal of the power transistor. The circuit may include a second buffer under the control of the switching controller circuit to further manage the operation of the power transistor.

Slew rate control for fast switching output stages

A circuit is provided that comprises a transformer having a first coil, which is arranged on a substrate, a second coil, which is arranged above the first coil on the substrate, and a dielectric between the first coil and the second coil. The circuit furthermore comprises a resonant circuit, which is couplable to the first coil and/or the second coil to form a resonant loop, wherein a measure of a characteristic frequency of the resonant loop and/or a measure of a power consumption of the resonant loop is able to be tapped off at an output of the resonant circuit. A corresponding method is also provided.

Circuit with transformer and corresponding method

Overload detection and protection for power switch circuits. For circuits with faster switching speed, fast fault detection and response to a detected overload condition may be desirable. Detection circuitry may monitor a voltage on the control terminal of one or more power switches. Based on empirical measurements, in an overload condition of a power switch circuit, e.g., a half-bridge circuit, the voltage at the control terminal may increase, and in some examples, increase to a magnitude that is greater than a supply voltage. A comparator may detect a voltage increase that exceeds a voltage magnitude threshold, output an indication to control circuitry for the power switch circuit, and the control circuitry may take action to protect the rest of the circuitry, such as reduce voltage or shut off the power switch circuit.

Diagnosis of gate voltage to detect high current

A method may comprise: controlling ON/OFF switching of a power switch via a driver circuit; receiving a first signal on a detection pin associated with the power switch, wherein the first signal corresponds to a first point in time when current is not passing through the power switch and wherein the first signal indicates a first voltage drop over one or more other circuit elements; receiving a second signal on the detection pin, wherein the second signal, wherein the second signal corresponds to a second point in time when current is passing through the power switch and wherein the second signal indicates a voltage drop over the power elements; and determining the voltage drop over the power switch based on a difference between the first signal and the second signal.

Techniques for measuring voltage over a power switch using zero current detection point

A circuit is provided, comprising a transformer having a first coil that is arranged on a substrate and a second coil that is arranged on the substrate above the first coil, and a dielectric between the first coil and the second coil. The circuit furthermore comprises a guard ring around the transformer. The circuit furthermore comprises a diagnostic circuit () that is configured so as to ground the guard ring in a normal operating mode and to measure a measurement voltage or a measurement current at a measurement impedance between the guard ring and the ground potential in a diagnostic operating mode.

Circuit containing a transformer and corresponding method

An example a circuit for controlling a power converter comprises a first power domain circuit including a first control circuit and a first driver circuit, wherein the first control circuit controls the first driver circuit to drive a first semiconductor device, wherein a second power domain circuit includes a second control circuit and a second driver circuit. The first control circuit is configured to receive a control signal for controlling the second driver circuit to drive a second semiconductor device; and identify, based on the control signal, a future electrical characteristic of a second power domain output of the power converter. Additionally, the first control circuit is configured to determine, based on the future electrical characteristic of the second power domain output of the power converter, whether to adjust one or more control parameters for controlling the first driver circuit to drive the first semiconductor device.

Analyzing a control signal in order to control a power converter to deliver energy to a load

In some examples, a device includes a capacitor arranged across the galvanic isolation barrier, where the capacitor is configured to communicate a single-ended signal from a first voltage domain to a second voltage domain. The device also includes a high-pass filter arranged in the second voltage domain and configured to receive the single-ended signal from the capacitor. The device further includes a low-pass filter arranged in the second voltage domain and coupled between the high-pass filter and a low-impedance node. The high-pass filter is coupled between the capacitor, the low-pass filter, and the low-impedance node, and the low-pass filter is configured to generate a differential signal.

Capacitive data transmission over a galvanic isolation

A driver device includes: a voltage terminal; a ground terminal; an output terminal; a first nMOS power transistor having a drain electrically connected to the voltage terminal, a source electrically connected to the output terminal, and a gate; an overvoltage protection circuit configured to limit a gate-to-source voltage of the first nMOS power transistor in a normal operating mode for the driver device; a pulldown circuit configured to force the first nMOS power transistor off in a stress test mode for the driver device; and a blocking circuit configured to block current flow from the output terminal to the ground terminal through the overvoltage protection circuit and the pulldown circuit in the stress test mode. A method of stress testing the driver device is also described.

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Esting, Germany

Marcus Nuebling