Koninklijke Philips Corporation N.v.

Interuniversitair Microelektronica Centrum (Imec)

Texas Instruments Corporation

Marcus Johannes Henricus Van Dal

Jacob Christopher Hooker

Robert James Lander

Jorge Adrian Kittl

Anabela Veloso

Tom Schram

Anne Lauwers

Anil Kottantharyil

A method for manufacturing a MOSFET device with a fully silicided (FUSI) gate is described. This method may be used to prevent formation of shorts between the FUSI gate and a contact to a source and/or a drain region. In particular, the method discloses the formation of an expansion volume above a gate dielectric. The volume is designed to substantially contain the fully silicided gate.

Method for forming a fully silicided gate and devices obtained thereof

A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the silicon region, a metal cluster layer from a first metal, such that, in the metal cluster layer, metal clusters alternate with sites where there are no metal clusters, the first metal being a non-siliciding metal at predetermined conditions, ii) depositing a metal layer of a second metal on top of the metal cluster layer, the second metal being a siliciding metal and iii) carrying out at least one heat treatment at the predetermined conditions on the second metal layer so as to form metal silicide through reaction of the second metal with the silicon region, wherein atoms of the first metal are displaced in a direction substantially perpendicular to the surface of the substrate.

Semiconductor device fabricated by a method of reducing the contact resistance of the connection regions

The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide. In one embodiment, those parts of the conductors which have different work functions are formed by etching a layer other than the silicon layer, in particular a metal layer, at the location of one of the two semiconductor structures. Furthermore, a further metal layer is applied over the silicon layer and is used to form a further metal silicide at the location of the second transistor. One embodiment of the invention is particularly suitable for use in CMOS technology and results in both PMOS and NMOS transistors with favorable properties.

Method for fabricating semiconductor devices having silicided electrodes

One embodiment of the invention relates to a method for fabricating a semiconductor device having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate. The method comprises forming a metal cluster layer from a first, non-siliciding metal, followed by the deposition of a metal layer consisting of a second, siliciding metal. A subsequent heat treatment is responsible for forming a metal silicide from the second metal, the atoms of the first metal being displaced in a direction substantially perpendicular to the surface of the substrate. According to one embodiment of the invention, the atoms of the first metal are displaced by the Kirkendall effect to beneath the metal silicide. If an MOST, for example, is being fabricated, this has advantages both at the location of the source and drain region and at the location of the gate electrode.

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Leuven, Belgium

Marcus Johannes Henricus Van Dal