Qorvo Us, Inc.

Rf Micro Devices, Inc.

Qoro Us, Inc.

Marcus Granger-Jones

Nadim Khlat

George Adrian Maxim

Baker P Scott

Dirk Robert Walter Leipold

Ruediger Bauder

Robert Aigner

Andrew F Folkmann

Brad Nelson

Ed Franzwa

Alexander Wayne Hietala

Christian Rye Iversen

Jean-Frederic Chiron

Kelvin Kai Tuan Yan

Jinsung Choi

Michael F Zybura

Ali Tombak

Mark Moffat

Julio C Costa

Daniel Charles Kerr

Jonathan Hale Hammond

Gernot G Fattinger

David K Cassetti

Jayanti Jaganatha Rao

Thomas Gregory Mckay

Jeffery Peter Ortiz

Eric K Bolton

Wayne Kennan

Yazid Yusuf

John Robert Siomkos

Steven R Bal

Toshiaki Moriuchi

Jeppe Korshøj Bendixen

Mark Alexander John Moffat

John Avery Capwell

Dirk Robert Walker Leipold

Jim Connelly

Group delay determination in a communication circuit is disclosed. The communication circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on a modulated voltage and a power management integrated circuit (PMIC) that generates the modulated voltage. Herein, the PMIC includes a group delay determination circuit to determine a relative group delay between the modulated voltage and a modulated current, which is internal to the power amplifier circuit and unknown to the PMIC, solely based on signals known to the PMIC. The determined relative group delay can help to time align the modulated voltage with the modulated current at the power amplifier circuit to improve error vector magnitude (EVM) and/or adjacent channel leakage ratio (ACLR). Further, by determining the relative group delay based on known signals to the PMIC, it is possible to achieve good time alignment between the modulated voltage and the modulated current.

Group delay determination in a communication circuit

A single pole double throw (SPDT) switch with embedded attenuators includes a transmitter attenuator circuit directly connected to a common input of the SPDT switch, and a receiver attenuator circuit directly connected to the common input of the SPDT switch. Switches in the transmitter attenuator circuit and in the receiver attenuator circuit are selectively or individually set to an open state or to a closed state to directly connect the transmitter attenuator circuit or the receiver attenuator circuit to the common input. The selective setting of the states of the switches also determines a given amount of attenuation for the transmitter attenuator circuit or the receiver attenuator circuit.

SPDT switches with embedded attenuators

A maximum current detection circuit with multiple input current ports and a maximum current port generates, on the maximum current port, a maximum current corresponding to the largest input current on one of the input current ports. The maximum current detection circuit includes multiple current mirror circuits, each controlled by one of the input currents. Each of the current mirror circuits includes outputs, each coupled to a respective one of the input current ports and the maximum current port. The current mirror circuit controlled by the largest input current becomes the dominant source for the input currents on each of the input current ports and also drives the maximum current on the maximum current port. The input currents may be single-ended or differential signals. The input currents may be respectively delayed signals of a windowing circuit in an envelope tracking circuit controlling a power amplifier of a wireless device.

Current mode multi-input maximum signal detector

A complementary envelope detector contemplates using two pair of mirrored transistors to provide a differential output envelope signal to an associated envelope tracking integrated circuit (ETIC) that supplies control voltages to an array of power amplifiers. While bipolar junction transistors (BJTs) may be used, other exemplary aspects use field effect transistors (FETs). In an exemplary aspect, a first pair are negative channel FETs (nFETs) and a second pair are positive channel FETs (pFETs).

Complementary envelope detector

A complementary balanced low-noise amplifier is disclosed. In one aspect, the low-noise amplifier (LNA) may be a single-ended cascoded complementary common-source LNA that is capable of operating in low-power conditions. In particular, the LNA may include a first path with a common-source amplifier formed from an N-type material and a second path with a common-source amplifier formed from a P-type material that collectively form a complementary common-source amplifier. By providing two paths in the complementary amplifier, headroom may be preserved for output transistors. Additionally, higher-order intercept points (e.g., IP2 or IP3) characteristics have better performance profiles resulting in better overall performance and improved user experience.

Complementary balanced low-noise amplifier circuit

Reversed semilattice filters with improved common mode rejection characteristics are disclosed. In one aspect, a filter may include two interior nodes coupled with an impedance that treats unwanted signals as common mode signals and provides rejection for common mode signals while passing differential signals of interest. The impedance is modified to have a resonant circuit that improves signal rejection in the stop band by lowering the effective impedance at those frequencies while leaving the pass band unaffected.

Reversed semilattice filter

A driving amplifier with low output impedance is disclosed. In one aspect, a driving amplifier stage that does not need an inter-stage impedance matching network between the driving amplifier stage and an output amplifier stage in a transmission chain may be achieved by providing stacking transconductance devices within the driving amplifier stage and reusing a supply current to provide an intermediate signal with high current but moderated voltage swing to drive the output amplifier stage. In specifically contemplated aspects, the stacked transconductance devices may be complementary metal oxide semiconductor (CMOS) field effect transistors (FETs).

Driving amplifier stage with low output impedance

A power management circuit operable with group delay is provided. In embodiments disclosed herein, the power management circuit includes a voltage processing circuit configured to receive a first time-variant target voltage having a first group delay relative to a time-variant target voltage and a second time-variant target voltage having a second group delay relative to the time-variant target voltage. Accordingly, the voltage processing circuit generates a windowed time-variant target voltage higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a group delay tolerance window(s) defined by the first group delay and the second group delay. As a result, the power management circuit can generate a time-variant voltage based on the windowed time-variant target voltage to help a power amplifier to avoid amplitude clipping when amplifying an analog signal.

Power management circuit operable with group delay

Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.

Systems and methods for providing an envelope tracking supply voltage

Maximum voltage detection in a power management circuit is provided. In embodiments disclosed herein, the power management circuit includes a voltage processing circuit configured to receive a first time-variant target voltage having a first group delay relative to a time-variant target voltage and a second time-variant target voltage having a second group delay relative to the time-variant target voltage. The voltage processing circuit includes a maximum signal detector circuit configured to generate a windowed time-variant target voltage that is higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a group delay tolerance window(s) defined by the first group delay and the second group delay. In this regard, the windowed time-variant target voltage can tolerate a certain amount of group delay within the group delay tolerance window(s).

Maximum voltage detection in a power management circuit

An inverted group delay circuit is provided. The inverted group delay circuit can offset a group delay between a pair of signals. In a non-limiting example, the inverted group delay circuit can be configured to offset a group delay (e.g., negative group delay) between a time-variant voltage and a time-variant envelope of an analog signal. More specifically, the inverted group delay circuit can output an inverted time-variant voltage having an opposing phase and time-adjusted relative to the time-variant voltage to thereby offset the group delay between the time-variant voltage and the time-variant envelope. As such, the inverted group delay circuit can be provided in a power management integrated circuit (PMIC) to improve timing alignment between a time-variant voltage(s) and a time-variant analog signal(s) at a power amplifier(s), thus helping to reduce potential amplitude distortion when the analog signal(s) is amplified by the power amplifier(s).

Inverted group delay circuit

An envelope tracking (ET) radio frequency (RF) front-end circuit is provided. The ET RF front-end circuit includes an ET integrated circuit(s) (ETIC(s)), a local transceiver circuit, a target voltage circuit(s), and a number of power amplifiers. The local transceiver circuit receives an input signal(s) from a coupled baseband transceiver and generates a number of RF signals. The target voltage circuit(s) generates a time-variant ET target voltage(s) based on the input signal(s). The ETIC(s) generates multiple ET voltages based on the time-variant ET target voltage(s). The power amplifiers amplify the RF signals based on the ET voltages. Given that the time-variant ET target voltage(s) is generated inside the self-contained ET RF front-end circuit, it is possible to reduce distortion in the time-variant ET target voltage(s), thus helping to improve operating efficiency of the power amplifiers, especially when the RF signals are modulated with a higher modulation bandwidth (e.g., &#x2265;200 MHz).

Envelope tracking radio frequency front-end circuit

An average power tracking (APT) power amplifier apparatus is provided. In a non-limiting example, the APT power amplifier apparatus includes multiple sets of power amplifier circuits configured to amplify a radio frequency (RF) signal(s) for transmission in different polarizations (e.g., vertical and horizontal). In examples disclosed herein, the APT power amplifier apparatus can be configured to employ a single power management integrated circuit (PMIC) to provide an APT voltage to all of the power amplifier circuits for amplifying the RF signal(s). By employing a single PMIC in the APT power amplifier apparatus, it is possible to reduce footprint, power consumption, and costs of the APT power amplifier apparatus.

Average power tracking power amplifier apparatus

RF circuitry, which includes a first acoustic RF resonator (ARFR) and a first compensating ARFR, is disclosed. A first inductive element is coupled between the first compensating ARFR and a first end of the first ARFR. A second inductive element is coupled between the first compensating ARFR and a second end of the first ARFR. The first compensating ARFR, the first inductive element, and the second inductive element at least partially compensate for a parallel capacitance of the first ARFR.

RF circuitry having simplified acoustic RF resonator parallel capacitance compensation

A power amplifier apparatus supporting reverse intermodulation product (rIMD) cancellation is provided. The power amplifier apparatus includes an amplifier circuit configured to amplify and output a radio frequency (RF) signal for transmission via an antenna port. The antenna port may receive a reverse interference signal, which may interfere with the RF signal to create a rIMD(s) that can fall within an RF receive band(s). A reverse coupling circuit is provided in the power amplifier apparatus to generate an interference cancellation signal based on the reverse interference signal. The amplifier circuit is configured to amplify the interference cancellation signal and the RF signal to create an intermodulation product(s) to suppress the rIMD(s) to a determined threshold. By suppressing the rIMD(s) in the power amplifier apparatus, it is possible to support concurrent transmissions and receptions in a number of RF spectrums while in compliance with stringent regulatory spurious emissions (SEM) requirements.

Growing community of inventors

Scotts Valley, CA, United States of America

Marcus Granger-Jones