International Business Machines Corporation

Marcos A Villarreal

Basu Vaidyanathan

Dean J Burdick

David Nevarez

Praveen Kalamegham

Debora Velarde

Bobbi A Brekke

Francisco Garcia

A system, method, and computer program product for expediting the identification of computer program code that is the source of errors in the execution of a computer program. A debugger monitors a specified memory address, or group of addresses for updates, during execution of the computer program. In response to determining that a running computer program has updated the memory address, the processor executes a watchpoint handler to identify the source of errors in a computer program executing in a data processing system. The watchpoint handler gathers trace information associated with the faulty processing thread, and records the trace information to a memory location. The watchpoint handler may also apply filters to the trace information to identify the source of the error, saving valuable debugging time.

Tracing memory updates and accesses for debugging computer programs

A system, method, and computer program product for managing processor entitlement of virtual processors in logical partitioned data processing system. One embodiment of the invention provides a method of managing processing resources in a data processing system. The method involves creating a resource set comprising a grouping of virtual processors, and allocating a processing resource entitlement the resource set. The method also includes assigning the resource set to a workload, receiving a request by the workload for utilization of processing resources, and in response to receiving the workload request dispatching the assigned resource set. The method further includes determining whether the dispatched virtual processors of the resource set have exceeded the assigned processing resource entitlement, and in response to determining that the processing resource entitlement has been exceeded, undispatching the resource set.

Allocation and regulation of CPU entitlement for virtual processors in logical partitioned platform

The different illustrative embodiments provide a method, apparatus, and computer program product for folding at each affinity level for a partition spanning multiple nodes. In one illustrative embodiment, a method is provided for identifying a number of domains in a number of affinity levels. A lightest loaded domain is identified in the number of domains identified. A number of nodes are identified in the lightest loaded domain identified. A lightest loaded node is identified in the number of nodes. A lightest loaded processing unit on the lightest loaded node is identified and the lightest loaded processing unit is folded.

Ensuring affinity at all affinity domains by folding at each affinity level possible for a partition spanning multiple nodes

A method, system and program are disclosed for automatically adjusting the allocation of a plurality of information processing system (IPS) resources among a plurality of logical partitions (LPARs). An LPAR is created on a first central processor complex (CPC) and a first LPAR identifier is generated. A configuration change manager is implemented on the LPAR to communicate changes in the LPAR's identifier to an automated resource manager (ARM). IPS resources are automatically allocated to the LPAR. If the LPAR is migrated a second CPC, a second LPAR identifier is similarly generated, resulting in an LPAR configuration change event. The ARM is notified that the migrated LPAR's identifier has changed and receives the changed LPAR identifier. Comparison operations are performed to determine whether the second LPAR identifier matches the first CPC. If not, resources allocated to the migrated LPAR are released for automated allocation to other LPARs comprising the first CPC.

Method of automated resource management in a partition migration capable environment

The present invention provides a computer that includes a processor part having a top side and a bottom side. A keyboard part, having a key side and back side, is pivotally connected to the processor part. The computer of the present invention includes a display part having a screen side and a back side. In some embodiments, the display part is pivotally connected to the processor part. In other embodiments, the display part is pivotally connected keyboard part. The keyboard part is configured to lie against the processor part in a closed position, with the key side of the keyboard part facing away from the top side of the processor part. The display part is configured to lie against and cover the keyboard part in the closed position, with the screen side of the display part facing toward the key side of the keyboard part. The display part is movable from the closed position to a first open position in which the keyboard part remains lying against the processor part with the key side of the keyboard part exposed. The keyboard part and the display part are movable to a second open position in which the display part lies against the processor part and the display part lies against the processor part.

Growing community of inventors

Austin, TX, United States of America

Marcos A Villarreal