Stmicroelectronics S.r.l.

St-ericsson Sa

Politecnico Di Milano

Stmicroelectronics International N.v.

Optis Circuit Technology, LLC

Stmicroelectron S.r.l.

Oct Circuit Technologies International Limited

Marco Zamprogno

Pierangelo Confalonieri

Francesca Girardi

Alberto Minuti

Germano Nicollini

Alireza Tajfar

Angelo Nagari

Pasquale Flora

Andrea Barbieri

Maurizio Bongiorni

Roberto Carminati

Luca Molinari

Giacomo Langfelder

Riccardo Martignone

Federico Guanziroli

Nicolo' Boni

Franco Consiglieri

Aldo Vidoni

Federico Garibaldi

Raffaele Enrico Furceri

Simone Zezza

Matteo Gianollo

Nicolò Boni

An input is coupled to a cathode of a laser diode having its anode coupled to a high-voltage-supply, with a cascoded current mirror having an input and output branches. The input branch is coupled between the high-voltage-supply and a sense resistor coupled to the input. The output branch is coupled between the high-voltage-supply and an output. A sense resistance is coupled between the output and ground, and includes a diode-coupled transistor coupled to the output and a resistor coupled between the diode-coupled transistor and ground. The input branch generates a current proportional to a voltage across the laser diode, and the output branch generates a mirrored current proportional to the current proportional to the voltage across the laser diode. A voltage proportional to the voltage across the laser diode is generated by the mirrored current flowing through the sense resistance. A comparison circuit compares this voltage to a threshold.

Laser driver incorporating clamping circuit with freewheeling diode

A pulsed signal generator generates a pulsed signal having a pulse width configured to be equal to a given fraction of a pulse width of a reference clock. A reference current source outputs current having a reference magnitude, and a comparison current source outputs current having a magnitude that is a function of the reference magnitude and the given fraction. A comparison circuit compares a total current output by one of the reference current source and the comparison current source during pulses of the reference clock to a total current output by the other of the reference current source and the comparison current source during pulses of the pulsed signal equal in number to the pulses of the reference clock in order to determine whether the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock.

Pulse width check circuit for laser diode pulse generator

A MEMS device includes a semiconductor body with a cavity and forming an anchor portion, a tiltable structure elastically suspended over the cavity, first and second support arms to support the tiltable structure, and first and second piezoelectric actuation structures biasable to deform mechanically, generating a rotation of the tiltable structure around a rotation axis. The piezoelectric actuation structures carry first and second piezoelectric displacement sensors. When the tiltable structure rotates around the rotation axis, the displacement sensors are subject to respective mechanical deformations and generate respective sensing signals in phase opposition to each other, indicative of the rotation of the tiltable structure. The sensing signals are configured to be acquired in a differential manner.

MEMS device with tiltable structure and improved control

A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a diode coupled between the input node and an output node, and an output capacitor coupled between the output node and ground such that an output voltage is formed across the output capacitor. A switch selectively couples the input node to ground in response to a drive signal. Control loop circuitry includes an error amplifier to generate an analog error voltage based upon a comparison of a feedback voltage to a reference voltage, the feedback voltage being indicative of the output voltage, a quantizer to quantize the analog error voltage to produce a digital error signal, and a drive voltage generation circuit to generate the drive signal as having a duty cycle based upon the digital error signal.

Control loop and efficiency enhancement for DC-DC converters

A method includes pre-charging a parasitic capacitance of a control node that is coupled to a control terminal of first and second transistors that have respective current paths that form a switched current path coupled between a load node and a storage node. Pre-charging the parasitic capacitance includes: making conductive a first auxiliary transistor that has a current path coupled between the storage node and the control node, or making conductive a second auxiliary transistor that has a current path coupled between the load node and the control node. The method further includes, after pre-charging the parasitic capacitance, making the switched current path conductive to couple the load node to the storage node.

Method of driving a capacitive load, corresponding circuit and device

A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.

Circuit for sensing an analog signal, corresponding electronic system and method

A bridge driver circuit applies a bias voltage across first and second input nodes of a resistive bridge circuit configured to measure a physical property such as pressure or movement. A sensing circuit senses drive current, bias current and common mode current for the bridge driver and sums the sensed currents to generate a source current. The source current is processed to determine a normalized resistance and temperature of the resistive bridge circuit and from which a temperature dependent sensitivity of the resistive bridge circuit is determined. A voltage output at first and second output nodes of the resistive bridge circuit is processed to determine a value of the physical property. This processing further involves applying a temperature correction in response to the determined temperature dependent sensitivity.

Resistive bridge sensor with temperature compensation

A level-shifter includes an input node coupled to a laser driver input receiving a trigger signal, the input node receiving a signal indicating generation of a laser drive-pulse. A p-channel transistor has a source coupled to a supply node, a drain coupled to an output node, and a gate coupled to the input node. An n-channel transistor has a drain coupled to the drain of the p-channel transistor, a source coupled to ground, and a gate coupled to the input node. A first switch couples the input node to the output node. Another p-channel transistor has a source coupled to the supply node, a drain coupled to the output node by a second switch, and a gate coupled to the input node. The first switch closes and second switch opens when the signal is low, and the first switch opens and second switch closes when the signal is high.

A pulsed signal generator generates a pulsed signal having a pulse width intended to be equal to a given fraction of a pulse width of a reference clock. A reference current source outputs current having a reference magnitude, and a comparison current source outputs current having a magnitude that is a function of the reference magnitude and the given fraction. A comparison circuit compares a total current output by one of the reference current source and the comparison current source during pulses of the reference clock to a total current output by the other of the reference current source and the comparison current source during pulses of the pulsed signal equal in number to the pulses of the reference clock in order to determine whether the pulse width of the pulse signal is less than or equal to the given fraction of the pulse width of the reference clock.

A charge recovery driver is for a pair of loads, and includes first and second output nodes coupled to a pair of loads. During an initial phase, the first output node is grounded and the second output node is tied to the supply voltage. During a first phase, the first output node is coupled to the first tank capacitor and the second output node is coupled to the second tank capacitor. During a second phase, the first and second output nodes are coupled to one another. During a third phase, the second output node is coupled to the first tank capacitor and the first output node is coupled to the second tank capacitor. During a fourth phase, the first output node is coupled to the supply voltage and the second output node is coupled to ground. The third, second, and first phases are then repeated in that order.

Charge recovery driver for MEMS mirror with reduced number of tank capacitors

A monostable circuit includes a delay cell with a reference generator generating a reference current based upon a PVT invariant resistance and a threshold voltage, and a delay block with an output capacitor and an output circuit altering an amount of charge stored on the output capacitor as a function of the reference current, in response to an input signal. An inverter has an input coupled to the output circuit. A logic circuit logically combines output of the inverter and the input signal to generate a monostable trigger pulse. The output circuit includes a current source sourcing the reference current to the output capacitor in response to a first logic state of an input signal, and a current sink sinking current from the output capacitor to discharge the output capacitor, in response to a second logic state of the input signal.

PVT compensated delay cell for a monostable

A method and apparatus for sensing a common mode feedback current are provided. The common mode feedback current may flow through a common mode resistive divider of a piezoresistive bridge. A first current mirror mirrors the common mode feedback current and provides a first mirrored common mode current. A current aggregation stage receives the first mirrored common mode current and determines a bridge current of the piezoresistive bridge based on the first mirrored common mode feedback current. A second current mirror may be used to mirror the first current mirror before determining the bridge current.

Fully differential operational amplifier common mode current sensing feedback

A circuit includes a capacitance coupled between a high voltage node and ground, a laser diode having an anode coupled to the high voltage node and a cathode coupled to an output node, and a current source coupled between the output node and ground. The current source turns on based on assertion of a trigger signal and sinks current from the capacitance to ground to thereby cause the laser diode to lase, and turns off based on deassertion of the trigger signal. A clamping circuit is coupled between the output node and the high voltage node, and clamps voltage at the output node occurring when the current source switches off.

A circuit includes a first transistor and a second transistor having respective control terminals coupled to receive first and second bias voltages. A first electronic switch is coupled in series with, and between current paths of the first and second transistors to provide an output current line between a circuit output node and ground. A second electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between a bias node and a charge transfer node in the output current line. A third electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between the charge transfer node and the control terminal of the second transistor.

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Cesano Maderno, Italy

Marco Zamprogno