Motorola Corporation

Marco Racanelli

Wen-Ling M Huang

Juergen A Foerstner

Bor-Yuan C Hwang

Heemyong Park

Hyungcheol Shin

Clifford I Drowley

Phillip H Williams

A method for forming an isolation structure ( ) on a SOI substrate ( ) is provided. A three layer stack of an etchant barrier layer ( ), a stress relief layer ( ), and an oxide mask layer ( ) is formed on the SOI substrate ( ). The three layer stack is patterned and etched to expose portions of the etchant barrier layer ( ). The silicon layer ( ) below the exposed portions of the etchant barrier layer ( ) is oxidized to form the isolation structure ( ). The isolation structure ( ) comprises a bird's head region ( ) with a small encroachment which results in higher edge threshold voltage. The method requires minimum over-oxidation and provides for an isolation structure ( ) that leaves the SOI substrate ( ) planar. Minimal over-oxidation reduces the number of dislocations formed during the oxidation process and improves the source to drain leakage of the device.

Reduced stress isolation for SOI devices and a method for fabricating

A semiconductor on insulator structure (50) includes a silicon layer (30) formed on an insulating substrate (20). The silicon layer (30) is partitioned into two sections (32, 34) which are electrically isolated from each other. The thickness of the silicon layer (30) in a first section (32) of the silicon layer (30) is adjusted independently from the thickness of the silicon layer (30) in a second section (34) of the silicon layer (30). Independently adjusting the thickness of the silicon layer (30) allows optimizing the performance of semiconductor devices (60, 80) fabricated in the first and second sections (32, 34) of the semiconductor on insulator structure (50).

Method for fabricating a semiconductor on insulator device

A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).

Method of forming an isolation oxide for silicon-on-insulator technology

A two stage threshold adjust implantation process is performed after field oxidation to avoid the effects of dopant redistribution and segregation. At any of several steps in a manufacturing process, only routine implant energy and dose adjustments are required to create a first and a second dopant profile (110, 120) that result in the reduction of edge leakage and threshold voltage sensitivity to device layer thickness of a semiconductor device on a semiconductor on insulator substrate.

Fabrication method for a semiconductor device on a semiconductor on

A silicon-on-insulator semiconductor device (40) having laterally-graded channel regions (23A, 24A) and a method of making the silicon-on-insulator semiconductor device (40). The silicon-on-insulator semiconductor device (40) has a gate structure (16) having sidewalls (19, 21) on a semiconductor layer (12). Lightly doped regions (26A, 27A) extend through an entire thickness of a portion of the semiconductor layer (12) under the sidewalls (19, 21). A laterally-graded channel region (23A) is formed below the gate structure (16) and abutting one (26A) of the lightly doped regions. A source (33) is formed in a first (26A) of the lightly doped regions and a drain region (34) is formed in a second (27A) of the lightly doped regions.

Semiconductor-on-insulator device having a laterally-graded channel

A method of adjusting a threshold voltage for a semiconductor device on a semiconductor on insulator substrate includes performing a threshold voltage adjustment implant (25) after formation of a gate structure (16) to reduce the diffusion of implanted dopant (26). Reducing dopant diffusion eliminates the narrow channel effect which degrades device performance. Implanting the dopant (26) after formation of the gate structure (16) simplifies processing of semiconductor device (28) by eliminating a photolithography step which is accomplished by utilizing photoresist (21) used for a source and drain implant (22).

Method of adjusting a threshold voltage for a semiconductor device

A semiconductor wafer (11) with a lattice mismatched film (12) on its upper surface is placed on a flat support surface (15). A laser beam (13, 23, 24, 26, 27) is directed onto the film (12). Curvature of the semiconductor wafer caused by the film (12) is measured simultaneously with film thickness based on characteristics of the reflected laser beam (23, 24, 26, 27). Strain within the film (12) is calculated from the curvature of the semiconductor wafer, film composition is calculated from the stress and thickness based on known properties of the film (12).

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Phoenix, AZ, United States of America

Marco Racanelli