Selex Sistemi Integrati S.p.a.

Selex Es S.p.a.

Marco Peroni

Alessio Pantellini

Claudio Lanzieri

Paolo Romanini

Simone Lavanga

Antonio Cetronio

A high electron mobility transistor comprising:

High electron mobility transistors with field plate electrode

Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region.

Method of manufacturing vertical pin diodes

The invention concerns a method of manufacturing a vertical PIN diode comprising: providing an epitaxial wafer comprising a vertically stacked N-type layer, intrinsic layer and P-type layer; forming an anode contact of the vertical PIN diode by forming an anode metallization on a first portion of the P-type layer defining an anode region; forming an electrically insulating layer around the anode region such that a first portion of the intrinsic layer extends vertically between the N-type layer and the anode region and second portions of the intrinsic layer extend vertically between the N-type layer and the electrically insulating layer; forming a trench in the electrically insulating layer and in the second portions of the intrinsic layer so as to expose a portion of the N-type layer defining a cathode region and to define a sacrificial side-guard ring consisting of a portion of the electrically insulating layer that extends laterally between the trench and the anode region and laterally surrounds said anode region; and forming a cathode contact of the vertical PIN diode by forming a cathode metallization on the exposed portion of the N-type layer defining the cathode region.

Disclosed herein is a pseudomorphic high electron mobility transistor (PHEMT) power device () including a semi-insulating substrate (); an epitaxial substrate () formed on the semi-insulating substrate () a contact layer (). The contact layer () includes a lightly doped contact layer () formed on the Schottky layer (), and a highly doped contact layer () formed on the lightly doped contact layer () and having a doping concentration higher than the lightly doped contact layer (). The PHEMT power device () further includes a&#x2014;wide recess () formed to penetrate the highly doped contact layer () and a narrow recess () formed in the wide recess () to penetrate the lightly doped contact layer (). The gate electrode () is formed in the narrow recess () and in Schottky contact with the Schottky layer ().

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Rome, Italy

Marco Peroni