Micron Technology Incorporated

Marco Onorato

Luca Porzio

Roberto Izzi

Nicola Colella

Erminio Di Martino

Ferdinando Pascale

Nadav Grosz

Andrea Vigilante

Sean L Manion

Massimo Zucchinali

Bryan D Butler

Alfredo Palazzo

Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

Reading sequential data using mapping information stored at a host device

Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Hardware reset management for universal flash storage

Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

Latency reduction of boot procedures for memory systems

Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

Commanded device states for a memory system

Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

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Villasanta, Italy

Marco Onorato