Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Marco Olivo

Luigi Pascucci

Marco MacCarrone

Silvia Padoan

Carla Maria Golla

Carla Maris Golla

Corrado Villa

Carlo Riva

Paolo Giuseppe Cappelletti

Alfonso Maurelli

Paolo Rosini

Sergio Pelagalli

Maurizio Peri

Marco Maccarrone

Alessandro Brigati

A method and device emulate the features of a EEPROM memory device. The device is included into a memory macrocell which is embedded into an integrated circuit comprising also a microcontroller. The device includes a Flash EEPROM memory structure formed by a predetermined number of sectors wherein at least two sectors of the Flash memory structure are used to emulate EEPROM byte alterability.

Flash EEPROM memory emulator of non-flash EEPROM device and corresponding method

A method is for self-test and correction of errors due to a loss charge for a flash memory including an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided. The method is implemented by realizing at least one additional row and at least one additional column of cells for each memory sector, storing parity codes in the additional row and column, and carrying out periodically a self-test routine and eventual correction routine including the following steps: repeating the sequential reading per bytes and parity check; verifying the consistency of the parity value with the value stored in the respective parity bit; and if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so identified is &ldquo;1&rdquo; reprogramming it to &ldquo;0&rdquo;.

Self-test and correction of loss of charge errors in a flash memory, erasable and programmable by sectors thereof

The invention relates to a matrix of memory cells for a semiconductor integrated microcontroller. The matrix is of the type intended for accommodation between macrocells of the microcontroller so as to reduce the needed circuit area on the semiconductor. The matrix comprises memory cells which are organized into rows and columns, with the number of columns defining the matrix height. The matrix height is advantageously variable according to the number of bits intended for selecting the matrix column, while its width is dependent on the overall capacity of the memory.

Memory cells matrix for a semiconductor integrated microcontroller

Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by simplifying the sensing process.

Anti-noise and auto-stand-by memory architecture

A circuit for detecting a reduction below a threshold value in a supply voltage provided to storage devices integrated into a semiconductor. A comparator is coupled between a voltage supply line and a signal ground and has a first or reference input and a second or test-signal input. A generator of a stable voltage reference has an output coupled to the first input and a divider of the supply voltage coupled to the second input of the comparator. A circuit means is arranged to feed the voltage supply line with the higher of the supply voltage and a programming voltage also provided to the storage devices.

Device for detecting a reduction in a supply voltage

A circuit architecture for testing a programmable logic matrix, e.g., the PLA type, has a group of input latches and a corresponding group of output latches connected to the matrix, and test information paths structured with at least one data bus and one address bus. The input latch and the output latch are connected electrically to the test data bus and to the test address bus to allow matrix testing with considerable time saving over known circuitry.

Method and apparatus for testing a network with a programmable logic

A count unit for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter and a number of registers equal in number to the count functions involved. The registers store the preceding count value and, when their content is to be incremented or in any way altered, load it into the counter which provides for performing the required operation, at the end of which, the content of the counter is stored in the respective register. One of the registers presents a second parallel input for externally loading an initial data which may be transferred to the other registers via the counter.

Count unit for nonvolatile memories

A circuit generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit includes a variable, asymmetrical propagation line composed of a succession of elementary delay elements enabled or disabled on the basis of memorized logic signals, the state of which is determined when debugging the memory in which the circuit is implemented.

Internal timing method and circuit for programmable memories

A device including a load connected by a selection circuit to a number of bit lines, and a load connected to a reference cell, for detecting the current in the selected bit line and in the reference cell. The load connected to the bit lines comprises a transistor, and the reference load comprises two current paths, each formed by one transistor. One of the two transistors is diode-connected, and the other is switchable by a switching network connected to the gate terminal of the respective transistor, for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

Reading circuit for an integrated semiconductor memory device

A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.

Regulation circuit and method for the erasing phase of non-volatile

A method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device with columns of memory elements grouped together to form portions of a bi-dimensional array of memory elements. The column redundancy circuitry comprises a plurality of non-volatile memory registers wherein each register is associated with a respective redundancy column of redundancy memory elements and each register is programmable to store an address of a defective column and an identifying code for identifying the portion of the bi-dimensional array to which the defective column belongs. When being programmed, each non-volatile memory register is supplied with column address signals and with a first subset of row address signals. The column address signals carry the address of a defective column and the first subset of row address signals carry the identifying code. One signal of a second subset of the row address signals is used to select one non-volatile memory register among the plurality of registers such that the defective column address and the identifying code carried by the column address signals and by the first subset of the row address signals are programmed into the selected non-volatile memory register. Using existing column and row address lines to program the redundancy memory registers reduces the need to generate dedicated on-chip signals, thereby minimizing the size of the memory device.

Method for programming redundancy registers in a column redundancy

A method for testing an electrically programmable non-volatile memory including a cell matrix and an internal state machine which governs the succession and timing of the memory programming phases includes excluding the internal state machine, modifying at least one of the control signals to program the cell matrix, and verifying programming correctness.

Method for programming and testing a nonvolatile memory

A circuit device for measuring the threshold voltage distribution among electrically programmable, non-volatile memory cells, which device comprises a differential amplifier having a first input connected to a first circuit leg including at least one memory cell and a second input connected to a second or reference circuit leg, and circuit means effective to cause an unbalance in the values of the currents flowing in the reference leg. The device is connected between a first supply voltage reference and a second voltage reference, and said circuit means comprise a generator of a varying current as a function of the supply voltage which is associated with the reference leg.

Threshold voltage measuring device for memory cells

An end-of-count detecting device for nonvolatile memories, comprising a decoder in the form of a wired OR structure of a number of transistors of the same type, the gate terminals of which are fed with a count signal generated by a counter element and having a predetermined end-of-count value to be detected. A load, which may be static, pseudo-dynamic or dynamic, is provided between the common node of the decoder transistors and a reference potential line; and the decoder output formed by the common node assumes a different logic level according to whether or not the end-of-count value coded by the wired OR structure is reached. A number of wired OR structures may be arranged side by side with an array of transistors for detecting a number of end-of-count values of the same counter element.

End-of-count detecting device for nonvolatile memories

A method for generating a reset signal in an electrically programmable non-volatile storage device of a type which comprises a matrix of memory cells and a control logic portion being supplied a supply voltage and a programming voltage, and a threshold detection circuit adapted to detect a decrease in the supply voltage, provides for the signal applied to the control logic to be obtained as a change-over function between the output signal from the threshold detector and a reset signal generated during the power-on transient of the device.

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Bergamo, Italy

Marco Olivo