Stmicroelectronics S.r.l.

Micron Technology Incorporated

Marco Messina

Antonino La Malfa

Salvatore Giove

Antonino Giuseppe La Spina

Vijay Malhi

Salvatore Polizzi

Antonino Capri'

Maurizio Francesco Perroni

Antonino Capri′

Giulio Mangione

Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory device, a request from the external device to access a storage area of the memory device and performing an unlock procedure of the storage area. The unlock procedure includes sending a first code from the memory device to the external device, and receiving a second code at the memory device from the external device. The second code is to be generated by a first encryption process performed on the first code to obtain the second code. The storage area is temporarily unlocked to allow the external device to access the storage area based on a determination that the received second code has a predetermined relationship to the first code. Additional apparatuses and methods are described.

Security memory access method and apparatus

A semiconductor memory may be provided with a built-in test mode that is accessible through a password protection scheme. This enables access to a built-in test mode after manufacturing, if desired. At the same time, the password protection prevents use of the built-in test mode to bypass security features of the memory.

Password protected built-in test mode for memories

A memory device includes: at least one storage area for storing data; a protection control structure adapted to selectively allow an external device access to the at least one storage area of the memory, the storage area being not freely accessible by the external device if protected; a control logic adapted to identify an access request by the external device to the at least one storage area and cooperating with the protection control structure for managing an unlock procedure for selectively granting the external device at least temporary access rights to the storage area if protected; means for providing a first code to the external device in said unlock procedure; means for receiving a second code from the external device in response to said first code; means for verifying validity of the received second code. The means for verifying validity are adapted to ascertain a correspondence of the second code with the first code based on a predetermined relationship. The control logic instructs the protection control structure to grant access to the storage area if the validity of the received second code has been verified. The first code issued by the memory device to the external device upon receiving an access request is changed after performing predetermined number of unlock procedures.

Enhanced security memory access method and architecture

A dual power supply digital device includes a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering a core part of the logic circuitry of the digital device. A second supply voltage source provides a second supply voltage for powering input buffers of the I/O pads of the digital device. A voltage translator latch stage may be powered at the regulated down converted first supply voltage for replicating a stored inverted replica of a logic value present on a respective I/O pad of the digital device onto an input node of a respective second input logic buffer powered at the regulated core supply voltage. The device may further include a transistor having a turn-on threshold coupling the input node of the second buffer to the regulated down converted core supply voltage, with the transistor having a control gate connected to the second power supply source.

Enhancement of power on reliability in a dual power supply digital device with down converter

A hybrid architecture for realizing a random numbers generator comprising a digital circuitry portion able to provide for a random bytes sequence as well as an analog circuitry portion able to provide a seed of the true random type is described.

Hybrid architecture for realizing a random numbers generator

Described herein is a method for soft-programming an electrically erasable nonvolatile memory device, wherein soft-programming is carried out with a soft-programming multiplicity equal to twice that used for writing data in the memory device until the current absorbed during soft-programming is smaller than or equal to the maximum current which is available for writing operations and which can be generated within the memory device, and with a soft-programming multiplicity equal to the one used for writing data in the memory device in the case where the current absorbed during soft-programming with double multiplicity is greater than the maximum current which is available for writing operations and which can be generated within the memory device.

Method for soft-programming an electrically erasable nonvolatile memory device, and an electrically erasable nonvolatile memory device implementing the soft-programming method

A random-bit sequence generator includes a biasing circuit, a source of a noisy voltage signal biased by the biasing circuit, an amplification stage generating an amplified signal representative of the sole non-zero-frequency (AC) component of the noisy voltage signal and an output stage electrically in cascade to the amplification stage that generates a random bit sequence in function of the amplified signal. The generator also filters the undesired low-frequency disturbance components because the amplification stage comprises an input low-pass filter that feeds the zero- (DC) component of the noisy voltage signal to one of the inputs of a differential amplifier, to another input of which is fed the non-filtered noisy voltage signal.

Random bit sequence generator

An electronic memory device monolithically integrated in semiconductor has a low pin count (LPC) serial interface. The memory device includes a memory cell array and associated row and column decode circuits. The memory device also includes a bank of T-latch registers to be addressed and accessed in a test mode for serially loading specific test data therein. The serially loading includes activating a test mode of operation by an address storage block for generating a corresponding signal, enabling the bank of T-latch registers in the device to serially receive a predetermined data set, and loading test data into the T-latch registers by using a LPC serial communication protocol.

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Augusta, Italy

Marco Messina