Sgs-Thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Maxim Integrated Products, Inc.

Marco Masini

Stefania Boiocchi

Edoardo Botti

Claudio Tavazzani

Sandro Storti

Federico Mazzarella

Luigi Franchini

Antonio Grosso

Antonio Chiriatti

Eric Labbe

Various embodiments of the invention provide for a buck-boost circuit that is immune against being stuck in an undesirable mode of operation. The circuit does not require any additional intermediate states other than buck-mode and boost-mode when managing transitions between buck and boost mode. In certain embodiments, a robust and simple buck-boost topology ensures efficient and rapid transitions by operating comparators that are coupled to switching elements of the buck-boost in such a manner that the inductor current can be selectively monitored to detect an inductor current slope during a power transfer phase. Information about the current slope enables a controller to make a decision whether a transition to another state is appropriate.

High efficiency buck-boost systems and methods

A class D amplifier includes an input integrating stage and a modulating stage for modulating the integrated input signal output by the integrating stage. The modulating stage uses as a carrier an alternate waveform of a frequency sufficiently higher than the frequency band of the analog input signal. The modulating stage further outputs a digital signal switching between a positive voltage and a negative voltage, and whose average value represents an amplified replica of the input analog signal. The class D amplifier further includes an output power stage producing an output digital signal. A feedback line including a resistor is connected between the output of the output power stage and an input node of an operational amplifier. The class D amplifier also includes a low-pass filter reconstructing an output analog signal, and a delay stage. The delay stage is functionally coupled in the direct path of propagation of the digital signal from the output of the modulating stage to an input of the output power stage. The delay stage delays the digital signal from the output of the modulating stage by a delay. The value of the delay is defined as a function of a desired broadening of the bandwidth and in consideration of the corresponding restriction of the range of variation of the duty cycle of the output digital signal.

Class-D amplifier with enhanced bandwidth

A constant limit duty-cycle is established by detecting the equivalent values VDD&prime; and &minus;VDD&Prime; of the voltages to which the output signal of the amplifier switches or pseudo supplies. An input limiting stage receiving an analog input signal utilizes the pseudo supply values VDD&prime; and &minus;VDD&Prime; as respective reference values for limiting the voltage swing of the analog signal output to a pre-defined fraction &agr;<1 of such reference values. This avoids using as a reference the real supply voltage values VDD and &minus;VDD, as commonly done. The constant limit duty cycle is substantially independent from fabrication process spreads, temperature, etc., and provides an optimal functioning of the final stage of the amplifier for all working conditions.

Constant duty-cycle limiting of analog input signal swing in a class-D amplifier

A low frequency PWM output bridge amplifier having an input network configurable for standard PWM digital input signals, phase shift PWM digital input signals or analog input signals and for standard PWM output or phase shift PWM output is provided. The amplifier includes two identical amplifying modules. One for the amplifying channel relative to the direct or positive PWM output and the other for the amplifying channel relative to the inverted or negative PWM output. Each module includes a switching output operational amplifier, having a voltage mode noninverting input, a current mode inverting input and a loop filter implementing a single or multiple slope integrator outputting a signal of a substantially triangular waveform. Each module also includes a logic inverter or a cascade of logic inverters coupled in cascade to the output of the integrator and outputting a logic PWM signal, an output power stage converting the logic PWM signal output by the inverter(s) in a PWM signal, switching between the potentials of the two supply rails of the circuit, and a feedback resistor connecting the output of power stage to the inverting input of the operational amplifier.

PWM bridge amplifier with input network configurable for analog or digital input not needing a triangular wave generator

A power supply regulator comprising a regulated-voltage source; a buffer connected to the voltage source; and a diode connected to the output of the buffer. A bootstrap capacitor is located between the diode and the output of a power stage; and the output of the power stage is switched between a low and a high value by a digital signal also supplied to the input of the buffer which therefore generates a switched regulated output voltage varying between a first value equal to the regulated voltage and a second lower value. The switched regulated voltage switches from the first to the second value before the output of the power stage switches to high, thus immediately disabling the diode and preventing current spikes due to minority carriers in the diode from being transmitted to the regulated-voltage source. The switched regulated voltage switches from the second to the first value before the output of the power stage switches to low, to permit charging of the bootstrap capacitor to the regulated voltage when the output is low.

Bootstrap line power supply regulator with no filter capacitor

An amplifier is formed by an astable multivibrator having a signal output supplying a two-state output signal to a power stage, that presents an output voltage (V.sub.o) switching between a first and second value. The output voltage presents a duty cycle varying with the input signal (V.sub.in) of the multivibrator. The amplifier, when connected between first and second supply lines that are symmetrical with respect to ground and are subject to supply noise, comprises a current source for generating the bias current of the astable multivibrator and supplying a current (I) that is switchable at each half cycle. The value of the current at each half cycle is proportional to the absolute value of the output voltage (V.sub.o) of the amplifier to vary the duty cycle of the amplifier in a manner correlated the supply noise, so that the average output voltage value is zero.

Single-output dual-supply class D amplifier

A single-pole negative feedback D-class amplifier having first and second input terminals for coupling to a signal source and an output terminal through which it transfers pulse modulated signals to a demodulating filter. A first resistor is feedback connected between the output terminal and an input circuit node connected to the second input terminal. A second resistor is connected between the input circuit node and the second input terminal. A capacitor is connected between the input circuit node and the first input terminal.

Single pole negative feedback for class-D amplifier

The circuit comprises: a pair of programmable cells connected in series, one conducting, the other one open, with one free terminal connected to the ground and the opposite free terminal connected to a supply voltage; a threshold circuit having one input connected to the node between the two programmable cells, a switching threshold lower than the difference between the supply voltage and the threshold voltage of one of the programmable cells, and an output adapted to assume one of two logic levels depending on whether the tension on the input is higher or lower than the threshold; and a first transistor which is connected between the ground and the opposite end of the pair of programmable cells, is normally off and has a gate which can be driven to make it conduct.

Growing community of inventors

Milan, Italy

Marco Masini