Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Micron Technology Incorporated

Other

Marco MacCarrone

Marco Olivo

Luigi Pascucci

Demetrio Pellicone

Giuseppe Giannini

Rino Micheloni

Carla Maria Golla

Giovanni Campardo

Jacopo Mulatti

Silvia Padoan

Stefano Ghezzi

Maurizio Branchetti

Stefano Commodaro

Guido Lomazzi

Andrea Ghilardelli

Ilaria Motta

Matteo Zammattio

Ignazio Martines

Carla Maris Golla

Donato Ferrario

Roberto Annunziata

Paolo Colombo

Vernon George McKenny

Marcelo Carrera

In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state.

Fast programming memory device

Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories.

Enhanced multilevel memory

Presented is an analog voltage value measuring device for measuring any of a set of voltage references that are generated inside a memory architecture. The selected voltage to be measured is connected to a facility line through a multiplexer. The memory architecture includes a set of output buffers connected to a respective set of output pads. The device also includes a converter block, connected between the facility line and the output buffers of the memory architecture for converting a measured analog value of a voltage reference selected by the multiplexer to a digital value, which is presented on the output pads. A method of measuring an analog voltage value in a memory device is also disclosed. The method includes selecting an analog voltage value from the set of voltage values; transferring the selected analog value onto the facility line; converting the selected analog value to a digital value; and presenting the digital value on the output pads.

Method and a device for measuring an analog voltage in a non-volatile memory

Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference. A method is also presented for generating voltage references with a reduced value of settling time as produced within a memory architecture.

Method and apparatus for generating from a single supply line voltages internal to a flash memory with reduced settling times

A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.

Low-consumption TTL-CMOS input buffer stage

An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.

ESD protection network for circuit structures formed in a semiconductor

An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.

Electronic counter for a non-volatile memory device integrated on a semiconductor

An electronic circuit generates a stable voltage signal for the polarization during a reading step of a UPROM redundancy cell incorporating at least one memory element of EPROM or Flash type, having at least one terminal to be polarized, and MOS transistors which connect such memory element to a low voltage power supply reference. The circuit includes a current mirror structure with a first control branch and a second output branch. The current mirror stricture includes a first series of MOS transistors (M,, M,, M,) in said first branch between the supply reference and a ground; and a second series of transistors (M,, M,, M,) in said second branch. The circuit also includes an input terminal connected to the gate terminal of a transistor of the first series of transistors and an output terminal corresponding to an interconnection node of the second series of transistors. The stable voltage is obtained through a current which passes through at least a pair of transistors of the second series.

Electronic circuit for generating a stable voltage signal for polarizing during a reading step UPROM memory cells operating at low feed voltage

Growing community of inventors

Palestro, Italy

Marco MacCarrone