International Business Machines Corporation

Marco Heddes

Ronald Pete Luijten

Antonius Paulus Engbersen

Andreas Guenther Herkersdorf

Ernst H Rothauser

Michel Colmant

Antonius J Engbersen

Marinus J Van Weert

Fast routing and non-blocking switch which accomodates multicasting and

The present invention relates to the management of a large and fast memory. The memory is logically subdivided into several smaller parts called buffers. A buffer-control memory (11) having as many sections for buffer-control records as buffers exist is employed together with a buffer manager (12). The buffer manager (12) organizes and controls the buffers by keeping the corresponding buffer-control records in linked lists. A request manager (20), as pad of the buffer manager (12), does or does not grant the allocation of a buffer. A stack manager (21) controls the free buffers by keeping the buffer-control records in a stack (23.1), and a FIFO manager (22) keeps the buffer-control records of allocated buffers in FIFO linked lists (23.2-23.n). The stack and FIFO managers (20), (21) are parts of the buffer manager (12), too.

High speed buffer management of share memory using linked lists and

The present invention relates to a data transmission system and concerns a method for transforming user frames into fixed length cells, e.g. ATM (Asynchronous Transfer Mode), such that the fixed length cells can be transported through a cell handling switch fabric (11). A hardware implementation of this method consists of two parts, a transmitter (12.1) and a receiver (13.1), both being part of a switching subsystem (10) comprising a switch fabric (11). The transmitter (12.1) buffers user data and segments them into fixed length cells to be transported through said switch (11). The receiver part (13.1) reassembles user data on reception of these cells.

Configurable gigabits switch adapter

The dynamic functional behavior of geographically distributed fast packet switching systems, including those which accommodate high-priority circuit switched traffic and low-priority packet switched traffic, are tested in real-time by sending test packets from one or more source nodes through the system to specific destinations that comprise a test packet analyzer. The test packets have the same structure as the data packets, but in their payload portion carry the entire information required to perform the testing. The nature of that test information depends on the characteristics of a set of predefined system errors the verification system is supposed to identify. For detecting errors, the test information would include an input address indicating the source of the test packet, a sequence number defining the order in which the packet should arrive at the destination, time bits relating to the packet length and/or to the expected packet transmission delay, and a cyclic redundancy code which covers the entire contents of the test packet, including its control portion. Each analyzer at a receiving station operates autonomously from the senders and processes all received traffic in real-time; this enables it to recognize all defined system errors, even those occurring with very low probability, at the packet level.

Method and apparatus for testing and evaluation of distributed networks

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Kilchberg, Switzerland

Marco Heddes