Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Cselt- Centro Studi E Laboratori Telecommunicazioni Spa

Sip - Societa Italiana Per L-esercizio Delle Telecomunicazioni P.a.

Sip - Societa Italiana Per L'esercizio Delle Telecommunicazioni

Marco Gandini

Alessandro Torielli

Andrea Finotello

Mauro Marchisio

Pierangelo Garino

Maura Turolla

Mario Sartori

Giovanni Ghigo

Vinicio Vercellone

Valter Bella

Gianmario Bollano

Luigi Licciardi

Ernesto Viale

Giovanni Baronetti

Fabio Bellifemine

Stefano Dal Lago

Frederich Mombers

Danilo Galgani

Dante Trevisan

Marco Mattavelli

Roberto Gaidano

Martin Gumm

Stephanie Dogimont

Didier Nicoulaz

A CAM memory is supplied targeted at storing data words whose bits can take on an indifferent logical value besides two complementary logical values. it includes a matrix (MA) of memory cells in which a pair of cells is assigned to each bit that can take on a ternary configuration. circuits (CT,. . . CT,, WR, SR; CT,. . . SR,, CT,. . . SR,) for memory (MA) matrix access control give access for performing comparisons during operation in the CAM mode or for writing/reading data by means of direct RAM mode addressing (FIG.,).

Content addressable memories

Circuit for motion estimation in digitized video sequence encoders

An integrated circuit for manipulating digitized video sequences is provided, for use in a system for transmission and reception of compressed video sequences to perform, possibly with the aid of an external memory, reordering, format conversion, prediction and motion compensation on the pictures in a sequence. The device has memory for temporarily storing sequences to be manipulated and data read from the external memory; a circuit for decoding information about the manipulations to be performed; address circuitry for transferring the data between the device and the external memory; circuitry for configuring the device by means of a remote processing unit; circuitry for processing the data read from the external memory; and circuitry for arranging the output sequences in the format required by the function to be performed. A controller may control, supervise and set up the functions to be performed.

Device for manipulating compressed video sequences

A device for transmitting and decoding audio-visual streams arranged in accordance with standard ISO/IEC 11172 is provided. The device (DEC) comprises: interfaces (CSC, IA, CIS) for connection to a local storage device (MEL) or to a telecommunications network (2, 3), for receiving streams from remote sources or send streams to remote receivers; demultiplexing and synchronisation means (DES) for splitting the audio-visual streams into constituent audio, video and private data streams and extracting synchronisation information from the streams, and means (DA, DV, UA, UV) for decoding audio and video streams and present audio and video signals in analog form at the output. A controller (CNT) is to control and supervise demultiplexing and decoding operations.

Device for transmitting, receiving and decoding compressed audiovisual

A high speed digital signal transceiver in CMOS technology, in which the receiver has a clock signal extraction circuit, which is capable of self-aligning on incoming data with no spurious locks. Utilizing the PLL technique, the circuit generates a clock signal locked to the incoming signal utilizing a local oscillator, voltage-controlled by two feedback loops, a main one for frequency and phase corrections and a secondary one for phase correction. Moreover, original circuit solutions for the phase detectors and the low-pass filters are also envisaged.

CMOS technology high speed digital signal transceiver

The switching element allows building up of ATM exchanges capable of processing cell flows at bit rates higher than 700 Mbit/s. It uses an architecture with output queues, implemented through a unique shared memory, suitably controlled in order to obtain spatial cell switching towards the outputs. ATM cells are converted into a highly parallel format by a structure named rotation memory, where through the cells are then transferred into the master memory. The rotation memory is used also for the inverse operations of format restoration towards the output. The element control circuit is entrusted with the generation of writing and reading addresses of the master memory, in order to carry out the switching proper.

High bit rate cell switching element in CMOS technology

An electronic circuit for generating error detection codes in digital sigs organized into serial data blocks, which derives the error code from the coefficients of a remainder polynomial obtained from the division of a dividend polynomial, whose coefficients are the bits of each serial block, and a convenient divisor polynomial. The circuit has a shift register wherein at the beginning of each serial data block the reset and the first datum load are performed in a single clock interval.

Electronic circuit for generating error detection codes for digital

An integrated circuit selectively programmable to form an active filter without external circuit components, the integrated circuit having 2.sup.m amplifying modules where m is an integer between 2 and 4, inclusive, p resistive matrices where p is 1 when m is other than 4 and is 2 when m=4, and a bias circuit, r of the amplifying modules being positioned in a first column separated from a second column of r amplifying modules by a respective one of the resistive matrices, where r=4 when m is other than 2 and r=2 when m=2, the second column of amplifying modules being separated from a third column of 4 amplifying modules when m=4 by a second of the resistive matrices.

Integrated active filter without external components

The circuit comprises two registers (SR12, SR8) which temporarily memorize uncompressed and compressed PCM words, respectively. The uncompressed word is sequentially read and a counter (CNT) counts the number of zeroes present in the most significant positions of the absolute value of the word. The compressed word is composed, in the corresponding register, of the sign bit of the uncompressed word, followed by the counting bits of the counter and by the bits of the positions of the uncompressed word following those of the counted zeroes.

PCM compression by encoding runs of zeroes

A transceiver inserted between a source of binary signals and a one-wire line, dialoguing with a similar transceiver in series with another source at the opposite end of the line, comprises two voltage sensors connected in parallel to the line at a point downstream of a terminal impedance at which the line voltage substantially equals the mean of the voltage levels simultaneously generated by the two sources. The two voltage sensors have thresholds respectively lying at a lower and an upper intermediate level between the two binary signal levels (L, H) employed and work into a common signal receiver through a multiplexer so controlled by the local source as to connect that receiver always to that detector whose low or high output signal corresponds to the binary value (L, H) of the signal then arriving from the remote source.

Digital transceiver for full-duplex transmission of binary signals over

A unit cell for a prefabricated semiconductor chip, to be converted into an array of logic gates by selective metallization, comprises two complementary pairs of MOSFETs occupying respective quadrants of a rectangular substrate area, with external gate contacts disposed in respective headers extending along the minor sides of the rectangle. Each header further contains two external channel (source or drain) contacts which with the two external gate contacts form a group of four input/output contacts. Two metallic strips serving as supply buses, parallel to the minor sides, are separated from the two headers by relatively narrow substrate zones so as to define a relatively wide central region between them. The external gate contacts of two diagonally opposite MOSFETs are interconnected by a strip of polycrystalline silicon crossing the supply buses, each of these buses being also crossed by a respective polysilicon strip linking the other external gate contact of the proximal contact group with an internal gate contact located in the central region. The two external channel contacts in each header, which are disposed near the corners of the cell area, are paired with respective internal contacts also located in the central region on correspondingly doped substrate portions, as are two other internal channel contacts each common to a respective transistor pair and located in an inner terminal section of its respective transistor pair which is separated from the associated outer terminal sections thereof by the polysilicon strips running between the associated external and internal gate contacts. A further polysilicon strip extends along one of the major sides of the cell area to facilitate certain intercell connections.

Unit cell for integrated-circuit gate arrays

A microprocessor associated with a PCM telecommunication network dialogues with remote data-handling components such as other microprocessors through message-interchange circuitry which includes a read/write memory having storage areas individually allocated to several PCM channels, one storage area serving to receive incoming messages destined for the local microprocessor while the remaining storage areas serve for the transmission of outgoing messages intended for respective remote components. A control unit, timed by signals from a synchronization extractor coupled to the network, communicates with the memory to detect state words written by the microprocessor into the memory to indicate the loaded or vacant condition of its storage areas. When the words of an outgoing message are asynchronously written by the local microprocessor into respective cells of a selected transmitting area, a corresponding state word causes the control unit to read out the message words synchronously to the network in the assigned time slot of consecutive PCM frames. Conversely, the words of an incoming message synchronously written into respective cells of the receiving area by the control unit, responding to the arrival of a distinctive start code, are asynchronously read out to the local microprocessor in response to a request signal from the latter.

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Turin, Italy

Marco Gandini