Micron Technology Incorporated

Intel Corporation

Numonyx B.v.

Marco Ferraro

Ferdinando Bedeschi

Claudio Resta

Rick K Dodge

Federica Ottogalli

Egidio Buda

Alessandro Cabrini

Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.

Methods and related devices for operating a memory array

Methods for phase-change memory array

Methods of operating memory arrays, as well as the memory arrays, are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern comprising both data hits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored, and writing the pattern to the memory array. Other methods of operation and memory devices are also described.

Methods of operating memory arrays are described. In various embodiments, a method includes determining a pattern to be written to a memory array, the pattern comprising both data bits having sensitive information to be stored and data bits having a state that is unimportant to the sensitive information to be stored, and writing the pattern to the memory array. Other methods of operation are also described.

Methods for operating a memory array

Methods for a phase-change memory array

According to a method for multilevel reading of a phase change memory cell a bit line () and a PCM cell () are first selected and a first bias voltage (V, V) is applied to the selected bit line (). A first read current (I), that flows through the selected bit line () in response to the first bias voltage (V, V), is compared with a first reference current (I). The first reference current (I) is such that the first read current (I) is lower than the first reference current (I), when the selected PCM cell () is in a reset state, and is otherwise greater. It is then determined whether the selected PCM cell () is in the reset state, based on comparing the first read current (I) with the first reference current (I). A second bias voltage (V, V), greater than the first bias voltage (V, V), is applied to the selected bit line () if the selected PCM cell () is not in the reset state.

Method for low-stress multilevel reading of phase change memory cells and multilevel phase change memory

Multilevel phase change memory cells may be programmed forming amorphous regions of amorphous phase change material in a storage region of the phase change memory cell. Crystalline paths of crystalline phase change material are formed through the amorphous regions of amorphous phase change material. Lengths of the crystalline paths are controlled so that at least a first crystalline path has a first length in a first programming state and a second crystalline path has a second length, different from the first length, in a second programming state.

Programming a multilevel phase change memory cell

A set bit in a phase change memory may be programmed to a reset bit using a series of pulses of increasing amplitude. An initial start pulse is applied. After the start pulse is applied, a check determines whether the bit has been reset. If not, a higher amplitude pulse is applied. Each time the pulse amplitude is to be incremented, a check determines whether a maximum safe pulse amplitude has been exceeded. The pulse amplitude is continually incremented until either the maximum is reached or all the bits to be programmed have been programmed into the correct reset state.

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Lecce, Italy

Marco Ferraro