Micron Technology Incorporated

Stmicroelectronics S.r.l.

Other

Marco Ferrario

Emanuele Confalonieri

Nicola Del Gatto

Daniele Balluchi

Christophe Vincent Antoine Laurent

Carlo Lisi

Francesco Mastroianni

Massimiliano Scotti

Marco Sforzin

Alessandro Magnavacca

Massimiliano Mollichelli

Claudio Nava

A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.

Timing violation handling in a synchronous interface memory

A phase-change memory includes a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, where an activate command starts and following activate commands are ignored until a preset time has elapsed.

Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain.

Indexed register access for memory device

A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.

Memory device employing three-level cells and related methods of managing

A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting the reaching of a threshold value by a current of each selected memory cell and of each reference cell, and means for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means for applying a controlled biasing current to the selected memory cells and to the at least one reference cell.

Memory device with a ramp-like voltage biasing structure based on a current generator

A method and circuit for programming a multilevel memory of a flash EEPROM type having a matrix of cells grouped in memory words. The method provides for the simultaneous generation of a first programming voltage value and a second verify voltage value to bias word lines of the memory matrix during programming and verify operations, respectively, of the memory itself. A circuit implementing the above method is also provided.

Programming method of multilevel memories and corresponding circuit

A device for timing random reading of a memory device with a data access time, in which reading is performed by a succession of consecutive operations, the timing device being designed to generate, for each operation, a corresponding timing signal such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration, which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration; the sum of the fixed durations being equal to the data access time of the memory device.

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Milan, Italy

Marco Ferrario